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119 条记录 (耗时 0.043 秒)

    Finfets having first and second gates of different resistivities
    51.
    发明授权
    Finfets having first and second gates of different resistivities 有权
    Finfets具有不同电阻率的第一和第二门

    公开(公告)号：US07268396B2

    公开(公告)日：2007-09-11

    申请号：US10937246

    申请日：2004-09-09

    申请人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  In-Soo Jung

    IPC分类号： H01L29/772

    CPC分类号： H01L29/785 ,  H01L21/823842 ,  H01L29/42384 ,  H01L29/66795

    摘要： A fin field effect transistor (FinFET) includes a first gate and a second gate. The first gate has a vertical part that is defined by sidewalls of a silicon fin and sidewalls of a capping pattern disposed on the silicon fin and a horizontal part horizontally extends from the vertical part. The second gate is made of a low-resistivity material and is in direct contact with the horizontal part of the first gate. A channel may be controlled due to the first gate, and a device operating speed may be enhanced due to the second gate. Related fabrication methods also are described.

    摘要翻译： 鳍状场效应晶体管（FinFET）包括第一栅极和第二栅极。 第一栅极具有由硅翅片的侧壁和设置在硅片上的封盖图案的侧壁限定的垂直部分，并且水平部分从垂直部分水平延伸。 第二栅极由低电阻率材料制成，并与第一栅极的水平部分直接接触。 由于第一门可以控制通道，并且由于第二门可能会增强设备运行速度。 还描述了相关的制造方法。

    Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers
    52.
    发明授权
    Methods of fabricating Fin-field effect transistors (Fin-FETs) having protection layers 有权
    制造具有保护层的Fin场效应晶体管（Fin-FET）的方法

    公开(公告)号：US07141456B2

    公开(公告)日：2006-11-28

    申请号：US10871742

    申请日：2004-06-18

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    IPC分类号： H01L21/84 ,  H01L21/332

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

    摘要翻译： 提供制造鳍场效应晶体管（Fin-FET）的方法。 翅片形成在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层形成在沟槽中，使得第一绝缘层的表面在鳍片的暴露在翅片的侧壁的表面下方凹进。 保护层形成在第一绝缘层上，并且第二绝缘层形成在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。 还提供了相关的Fin-FET。

    Method and device for forming an STI type isolation in a semiconductor device
    53.
    发明授权
    Method and device for forming an STI type isolation in a semiconductor device 失效
    在半导体器件中形成STI型隔离的方法和装置

    公开(公告)号：US06660613B2

    公开(公告)日：2003-12-09

    申请号：US10102997

    申请日：2002-03-22

    申请人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    发明人： Chul-Sung Kim ,  Si-Young Choi ,  Jung-Woo Park ,  Jong-Ryol Ryu ,  Byeong-Chan Lee

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.

    摘要翻译： 半导体器件中的沟槽隔离及其制造方法包括：在硅衬底中形成具有用于器件隔离的内侧壁的沟槽; 在形成沟槽的内侧壁的硅衬底的表面上形成氧化物层; 向硅衬底提供愈合元件以去除悬挂键; 并用器件隔离层填充沟槽，从而形成沟槽隔离，而不产生悬挂键导致电荷陷阱。

    Method of manufacturing a non-volatile memory device
    56.
    发明授权
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US08114735B2

    公开(公告)日：2012-02-14

    申请号：US11902209

    申请日：2007-09-20

    申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

    发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

    摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

    摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

    MICROWAVE OVEN
    57.
    发明申请
    MICROWAVE OVEN 有权
    微波炉

    公开(公告)号：US20110147378A1

    公开(公告)日：2011-06-23

    申请号：US12935804

    申请日：2009-04-01

    申请人： Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

    发明人： Sang-Ryul Lee ,  Kyu-Young Kim ,  Jae-Myung Chin ,  Dong-Han Kim ,  Si-Young Choi ,  Sung-Ho Choi

    IPC分类号： H05B6/64

    CPC分类号： H05B6/708

    摘要： A microwave oven includes a cavity having a cooking chamber; a magnetron oscillating microwave radiation used for cooking food in the cooking chamber; and a plurality of radiation openings through which the microwave radiation is radiated into the cooking chamber, each of the radiation openings having a length in a direction where the microwave radiation is guided by a waveguide, the length being greater or less than λ/4.

    摘要翻译： 微波炉包括具有烹饪室的空腔; 用于在烹饪室中烹饪食物的磁控管振荡微波辐射; 以及多个辐射开口，微波辐射通过该辐射开口辐射到烹饪室中，每个辐射开口具有在微波辐射被波导引导的方向上的长度，该长度大于或小于λ/ 4。

    METHOD AND APPARATUS FOR DEPOSITION OF DIFFUSION THIN FILM
    58.
    发明申请
    METHOD AND APPARATUS FOR DEPOSITION OF DIFFUSION THIN FILM 审中-公开
    用于沉积薄膜沉积的方法和装置

    公开(公告)号：US20110114474A1

    公开(公告)日：2011-05-19

    申请号：US12743706

    申请日：2007-11-22

    申请人： Sang-Youl Bae ,  Si-Young Choi ,  Sung-Youp Chung ,  Jung-Hyun Choi

    发明人： Sang-Youl Bae ,  Si-Young Choi ,  Sung-Youp Chung ,  Jung-Hyun Choi

    IPC分类号： C23C14/34 ,  C23C14/22 ,  C23C14/14 ,  C23C14/54

    CPC分类号： C23C14/0641 ,  C23C14/325 ,  C23C14/345 ,  H01J37/34

    摘要： This invention relates to a method and apparatus for deposition of a diffused thin film, useful in the fabrication of semiconductors and for the surface DC-Bias coating of various tools. In order to coat the surface of a treatment object, such as semiconductors, various molded products, or various tools, with a thin film, one or more process factors selected from among a bias voltage, a gas quantity, an arc power, and a sputtering power are continuously and variably adjusted, whereby the composition ratio of the thin film which is formed on the surface of the treatment object not through a chemical reaction but through a physical method is continuously varied, thus manufacturing a thin film having high hardness. The composition ratio of the thin film to be deposited is selected depending on the end use thereof, thereby depositing the thin film having superior wear resistance, impact resistance, and heat resistance.

    摘要翻译： 本发明涉及一种沉积扩散薄膜的方法和装置，可用于制造半导体和各种工具的表面直流偏置涂层。 为了涂覆诸如半导体，各种模制产品或具有薄膜的各种工具的处理对象的表面，从偏置电压，气体量，电弧功率和 溅射功率被连续且可变地调节，由此，不是通过化学反应而是通过物理方法形成在处理对象表面上的薄膜的组成比不断变化，因此制造具有高硬度的薄膜。 要沉积的薄膜的组成比根据其最终用途来选择，从而沉积具有优异的耐磨性，耐冲击性和耐热性的薄膜。