公开(公告)号：US06791360B2

公开(公告)日：2004-09-14

申请号：US10241202

申请日：2002-09-11

申请人： Claude R. Gauthier ,  Brian W. Amick ,  Aninda Roy

发明人： Claude R. Gauthier ,  Brian W. Amick ,  Aninda Roy

IPC分类号： H03K1900

CPC分类号： H03L7/07 ,  G06F9/3869 ,  H03K5/133 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0041

摘要： A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

公开(公告)号：US06759877B1

公开(公告)日：2004-07-06

申请号：US10337523

申请日：2003-01-07

申请人： Shaishav A. Desai ,  Claude R. Gauthier ,  Anup S. Mehta

发明人： Shaishav A. Desai ,  Claude R. Gauthier ,  Anup S. Mehta

IPC分类号： H03K1920

CPC分类号： H03K19/0963 ,  H03K19/00384

摘要： A method and apparatus that dynamically control an amount of offset current generated by a keeper device are provided. Further, a method and apparatus that use a temperature-controlled keeper device to dynamically optimize an evaluation performance of a dynamic circuit are provided. In particular, when IC temperature is relatively high, i.e., there is increased current leakage in the dynamic circuit, an amount of offset current output by the temperature-controlled keeper may be increased, thereby preventing a dynamic node of the dynamic circuit from being discharged, or otherwise adversely affected, by the increased current leakage. Alternatively, when the IC temperature is relatively low, i.e., there is decreased current leakage in the dynamic circuit, the amount of offset current output by the temperature-controlled keeper may be decreased, thereby ensuring that the offset current is not so large that it severely degrades the evaluation performance.

摘要翻译： 提供了一种动态地控制由保持装置产生的偏移电流量的方法和装置。 此外，提供了使用温度控制保持装置来动态优化动态电路的评估性能的方法和装置。 特别地，当IC温度相对较高时，即动态电路中的电流泄漏增加时，由温度控制保持器输出的偏移电流量可能会增加，从而防止动态电路的动态节点放电 ，或以其他方式不利地受到电流泄漏的影响。 或者，当IC温度相对较低时，即动态电路中的电流泄漏减少时，由温度控制的保持器输出的偏移电流量可能会降低，从而确保偏移电流不会大到 严重降低评估绩效。

公开(公告)号：US06734716B2

公开(公告)日：2004-05-11

申请号：US10247127

申请日：2002-09-19

申请人： Brian W. Amick ,  Lynn Warriner ,  Claude R. Gauthier ,  Tri Tran

发明人： Brian W. Amick ,  Lynn Warriner ,  Claude R. Gauthier ,  Tri Tran

IPC分类号： G05F110

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K19/0175

摘要： A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

摘要翻译： 提供了使用电压调节器产生“虚拟”电源的SSTL存储器接口预驱动器级。 低于预驱动级的电源电压的“虚拟”电源允许使用低压晶体管，从而提高接口性能并降低系统功耗。 预驱动器级使用偏置电路来偏置由以源极跟随器配置布置的晶体管形成的稳压器，以产生预驱动器级的电压转换器级工作的“虚拟”电源，以产生输出 的前驱动阶段。

公开(公告)号：US06701488B2

公开(公告)日：2004-03-02

申请号：US09992607

申请日：2001-11-14

申请人： Brian W. Amick ,  Claude R. Gauthier ,  Tyler Thorp

发明人： Brian W. Amick ,  Claude R. Gauthier ,  Tyler Thorp

IPC分类号： G06F1750

CPC分类号： H03K19/00361

摘要： A method for reducing noise in an I/O system has been developed. The method includes powering up the I/O supply and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the I/O power supply, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.’

摘要翻译： 已经开发了用于减少I / O系统中的噪声的方法。 该方法包括上电I / O电源，并在电源端子上激活或插入分流电阻。 分流电阻与I / O电源并联插入，并且可控制，使得电阻可以选择性地“接通”和/或“关闭”。

公开(公告)号：US06686785B2

公开(公告)日：2004-02-03

申请号：US09975359

申请日：2001-10-11

申请人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

发明人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

IPC分类号： H03L706

CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。

公开(公告)号：US06570420B1

公开(公告)日：2003-05-27

申请号：US10230649

申请日：2002-08-29

申请人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

发明人： Pradeep R. Trivedi ,  Claude R. Gauthier ,  Dean Liu

IPC分类号： H03L706

CPC分类号： H03L7/0891 ,  H03L7/0812

摘要： A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes a programmable current source that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. The programmable current source includes at least one current source and switch to adjust the leakage current offset circuit. The programmable current source is selectively adjusted by a combinational logic circuit. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after fabrication of the adjustable delay locked loop.

摘要翻译： 提供了延迟锁定环路漏电流的制造后调整方法和装置。 调节系统包括一个可编程电流源，调节漏电流补偿电路以补偿电容器的漏电流。 电容器连接到延迟锁定环路的控制电压。 可编程电流源包括至少一个电流源和用于调整漏电流补偿电路的开关。 可编程电流源由组合逻辑电路选择性地调节。 对延迟锁定环路中的漏电流的这种控制允许设计者在制造可调延迟锁定环路之后实现期望的延迟锁定环路工作特性。

公开(公告)号：US06462604B1

公开(公告)日：2002-10-08

申请号：US09847495

申请日：2001-05-02

申请人： Brian W. Amick ,  Claude R. Gauthier

发明人： Brian W. Amick ,  Claude R. Gauthier

IPC分类号： H03K1716

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A circuit for reducing the noise associated with a clock signal for a flip-flop based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal.

摘要翻译： 已经开发了用于减少与基于触发器的电路的时钟信号相关联的噪声的电路。 电路包括充电控制部分，其在时钟周期的预定时间内存储电荷，以及在时钟周期的预定时间内释放所存储的电流的转储控制部分。 电荷被释放到由时钟信号服务的系统的电网上。

公开(公告)号：US06456107B1

公开(公告)日：2002-09-24

申请号：US09754573

申请日：2001-01-04

申请人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

发明人： Claude R. Gauthier ,  Tyler J. Thorp ,  Richard L. Wheeler ,  Brian Amick

IPC分类号： H03K19003

CPC分类号： H02M3/00 ,  H02M1/44 ,  H02M3/07

摘要： A method for regulating resonance in a micro-chip has been developed. The circuit includes an on-chip de-coupled capacitor that is shunted across the supply and ground voltages, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

摘要翻译： 已经开发了用于调节微芯片中的共振的方法。 该电路包括一个在电源和接地电压上分流的片上去耦合电容器，以及一个在电源和接地电压上与电容并联的带通分流调节器。 调节器将以预定频率将电源和接地电压短路，以减少对微芯片的共振效应。

公开(公告)号：US06392443B1

公开(公告)日：2002-05-21

申请号：US09504508

申请日：2000-02-15

申请人： Claude R. Gauthier

发明人： Claude R. Gauthier

IPC分类号： H03K1994

CPC分类号： H03K5/01

摘要： A method which allows for a more efficient pre-emphasis of a high frequency inter-chip signal. The method uses a single predriver stage to equalize a signal when a transition in value of a digital signal is detected. The method equalizes the signal with decreased power and area requirements for greater efficiency.

摘要翻译： 允许高频片间信号的更有效的预加重的方法。 当检测到数字信号的值转换时，该方法使用单个预驱动级来均衡信号。 该方法使功率和面积要求降低，从而提高效率。

公开(公告)号：US06377076B1

公开(公告)日：2002-04-23

申请号：US09503144

申请日：2000-02-15

申请人： Claude R. Gauthier

发明人： Claude R. Gauthier

IPC分类号： H03K190175

CPC分类号： H04L25/085 ,  H04L25/0286 ,  H04L25/03343 ,  H04L25/03878

摘要： A circuit which allows for a more efficient pre-emphasis of a high frequency inter-chip signal. The circuit uses a single predriver stage to equalize a signal when a transition in value of a digital signal is detected. The circuit equalizes the signal with decreased power and area requirements for greater efficiency.

摘要翻译： 允许更高效的预加重高频片间信号的电路。 当检测到数字信号的值转换时，电路使用单个预驱动级来均衡信号。 该电路使功率和面积要求降低，从而提高了效率。