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51.发明授权Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries 失效SMP系统总线的精确同步机制，使用标记的窥探操作来避免重试
公开(公告)号：US6029204A
公开(公告)日：2000-02-22
申请号：US815648
申请日：1997-03-13
CPC分类号： G06F9/52
摘要： A method of synchronizing an initiating processing unit in a multi-processor computer system with other processing units in the system, by assigning a unique tag for each processing unit, and issuing synchronization messages which include the unique tag of an initiating processing unit. The processing units each have a snoop queue for receiving snoop operations and corresponding tags associated with instructions issued by an initiating processing unit, and the processors examine their respective snoop queues to determine whether any snoop operation in those queues has a tag which is the unique tag of the initiating processing unit. A retry message is sent to the initiating processing unit from any of the other processing units which determine that a snoop operation in a snoop queue has a tag which is the unique tag of the initiating processing unit. In response to the retry message, the initiating processing unit re-issues the synchronization message, and the other processors re-examine their respective snoop queues, in response to the re-issuing of the synchronization message, to determine whether any snoop operation in those queues still has a tag which is the unique tag of the initiating processing unit.
摘要翻译： 一种将多处理器计算机系统中的发起处理单元与系统中的其他处理单元同步的方法，通过为每个处理单元分配唯一标签，以及发出包括发起处理单元的唯一标签的同步消息。 处理单元各自具有用于接收窥探操作的窥探队列和与由发起处理单元发出的指令相关联的对应标签，并且处理器检查它们各自的窥探队列以确定这些队列中的任何窥探操作是否具有作为唯一标签的标签 的启动处理单元。 重试消息从确定窥探队列中的窥探操作具有作为发起处理单元的唯一标签的标签的任何其他处理单元发送到发起处理单元。 响应于重试消息，发起处理单元重新发布同步消息，并且其他处理器响应于重发同步消息而重新检查其相应的窥探队列，以确定是否有任何窥探操作 队列仍然具有作为启动处理单元的唯一标签的标签。
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52.发明授权Method and system for transferring data between buses having differing ordering policies 失效在具有不同排序策略的总线之间传送数据的方法和系统
公开(公告)号：US6014721A
公开(公告)日：2000-01-11
申请号：US4145
申请日：1998-01-07
CPC分类号： G06F13/4013
摘要： A method and apparatus for ordering operations and data received by a first bus having a first ordering policy according to a second ordering policy which is different from the first ordering policy, and for transferring the ordered data on a second bus having the second ordering policy. The system includes a plurality of execution units for storing operations and executing the transfer of data between the first and second buses. Each one of the execution units are assigned to a group which represent a class of operations. The apparatus further includes intra prioritizing means, for each group, for prioritizing the stored operations according to the second ordering policy exclusive of the operation stored in the other group. The system also includes inter prioritizing means for determining which one of the prioritized operations can proceed to execute according to the second ordering policy.
摘要翻译： 一种用于对具有根据与第一排序策略不同的第二排序策略的第一排序策略的第一总线接收的操作和数据的方法和装置，以及用于在具有第二排序策略的第二总线上传送有序数据。 该系统包括用于存储操作并执行第一和第二总线之间的数据传送的多个执行单元。 每个执行单元被分配给表示一类操作的组。 该装置还包括针对每个组的内部优先级装置，用于根据除了存储在另一组中的操作之外的第二排序策略对所存储的操作进行优先级排序。 该系统还包括用于根据第二排序策略确定优先操作中的哪一个可以继续执行的区间优先化装置。
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53.发明授权
公开(公告)号：US5978871A
公开(公告)日：1999-11-02
申请号：US834114
申请日：1997-04-14
CPC分类号： G06F12/0893 , G06F13/1668
摘要： Cache and architectural specific functions within a cache controller are layered to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster.
摘要翻译： 高速缓存控制器中的缓存和架构特定功能被分层，以允许将复杂操作分成等效的简单操作。 因此，基础操作的架构变体可以被分配到不同的缓存和架构操作中并分开处理。 因此，支持复杂操作的逻辑可以被简化并且运行得更快。
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54.发明授权System and method for completing full updates to entire cache lines stores with address-only bus operations 有权使用仅地址总线操作完成对整个高速缓存行存储的完全更新的系统和方法公开(公告)号：US07493446B2
公开(公告)日：2009-02-17
申请号：US12034769
申请日：2008-02-21
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。
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55.发明授权Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction 失效用于通过执行指令获取多个全球推广设施的方法，装置和系统公开(公告)号：US06842847B2
公开(公告)日：2005-01-11
申请号：US10268744
申请日：2002-10-10
CPC分类号： G06F12/084 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/1433 , Y10S707/99938
摘要： A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first processor executes a single acquisition instruction to concurrently acquire a plurality of promotion bit fields exclusive of at least the second processor. In response to execution of the acquisition instruction, the first processor receives an indication of success or failure of the acquisition instruction, wherein the indication indicates success of the acquisition instruction if all of the plurality of promotion bit fields were concurrently acquired by the first processor and indicates failure of the acquisition instruction if fewer than all of the plurality of promotion bit fields were acquired by the first processor.
摘要翻译： 多处理器数据处理系统包括耦合到互连的第一和第二处理器以及包含多个提升位字段的全局推广设备。 第一处理器执行单个采集指令以同时获取排斥至少第二处理器的多个升级位字段。 响应于所述获取指令的执行，所述第一处理器接收所述获取指令的成功或失败的指示，其中如果所述多个提升位字段是由所述第一处理器同时获取的，则所述指示指示所述获取指令的成功，以及 指示如果所述第一处理器获取的所述多个提升位字段中的少于全部，则所述获取指令失败。
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56.发明授权Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction 失效使用无数据交易获取全球推广设施的方法，装置和系统公开(公告)号：US06829698B2
公开(公告)日：2004-12-07
申请号：US10268727
申请日：2002-10-10
IPC分类号： G06F946
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0811 , G06F12/0815 , Y10S707/99938 , Y10S707/99952
摘要： A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor among the plurality of processors, the first processor transmits an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility exclusive of at least a second processor among the plurality of processors. In response to receipt of a combined response for the address-only operation representing a collective response of others of the plurality of processors to the address-only operation, the first processor determines whether or not acquisition of the promotion bit field was successful by reference to the combined response.
摘要翻译： 数据处理系统包括全球推广设施和通过互连耦合的多个处理器。 响应于多个处理器中的第一处理器执行获取指令，第一处理器在互连上发送仅地址操作，以在全球推广设备之内获取不包括至少第二处理器的促销位字段 多个处理器。 响应于接收到仅地址操作的组合响应，其表示多个处理器中的其他处理器的集合响应到仅地址操作，则第一处理器通过参考获取促销位字段的获取是否成功 综合反应。
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57.发明授权Symmetric multiprocessor systems with an independent super-coherent cache directory 失效具有独立超级相干缓存目录的对称多处理器系统公开(公告)号：US06779086B2
公开(公告)日：2004-08-17
申请号：US09978363
申请日：2001-10-16
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system comprising, in addition to a first and second processor having an respective first and second cache and a main cache directory affiliated with the first processor's cache, a secondary cache directory of the first cache, which contains a subset of cache line addresses from the main cache directory corresponding to cache lines that are in a first or second coherency state, where the second coherency state indicates to the first processor that requests issued from the first processor for a cache line whose address is within the secondary directory should utilize super-coherent data currently available in the first cache and should not be issued on the system interconnect. Additionally, the cache controller logic includes a clear on barrier flag (COBF) associated with the secondary directory, which is set whenever an operation of the first processor is issued to said system interconnect. If a barrier instruction is received by the first processor while the COBF is set, the contents of the secondary directory are immediately flushed and the cache lines are tagged with an invalid state.
摘要翻译： 一种多处理器数据处理系统，除了具有相应的第一和第二高速缓存以及隶属于第一处理器的高速缓存的主缓存目录的第一处理器和第二处理器之外，还包括第一高速缓存的副高速缓存目录，其包含高速缓存行的子集 来自对应于处于第一或第二相关性状态的高速缓存行的主缓存目录的地址，其中第二一致性状态向第一处理器指示从第一处理器发出的对于地址在次目录内应该利用的高速缓存行的请求 超级相干数据目前在第一个缓存中可用，不应在系统互连上发布。 此外，高速缓存控制器逻辑包括与副目录相关联的清除屏障标志（COBF），其随着第一处理器的操作被发布到所述系统互连而被设置。 如果在设置COBF时由第一处理器接收到屏障指令，则立即刷新副目录的内容，并将高速缓存行标记为无效状态。
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公开(公告)号：US06763435B2
公开(公告)日：2004-07-13
申请号：US09978355
申请日：2001-10-16
IPC分类号： G06F1314
CPC分类号： G06F12/0831
摘要： A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.
摘要翻译： 一种用于提高多处理器数据处理系统的性能的方法，包括：窥探在所述数据处理系统的系统总线上的共享高速缓存行中保存的数据的请求，所述数据处理系统的高速缓存包含所述共享高速缓存行的更新副本，并响应于所述 第二处理器的请求，在系统总线上发出第一响应，向请求处理器指示请求处理器可以利用当前存储在请求处理器的高速缓存的共享高速缓存行中的数据。 当请求被第二处理器窥探并且第二处理器决定释放到请求处理器的高速缓存行上的锁时，第二处理器在系统总线上发出指示第一处理器应该利用新的/相干数据的第二响应， 那么第二处理器将锁定释放到第一处理器。
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59.发明授权Data processing system and method for resolving a conflict between requests to modify a shared cache line 失效用于解决修改共享缓存行的请求之间的冲突的数据处理系统和方法公开(公告)号：US06763434B2
公开(公告)日：2004-07-13
申请号：US09752947
申请日：2000-12-30
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Disclosed herein are a data processing system and method of operating a data processing system that arbitrate between conflicting requests to modify data cached in a shared state and that protect ownership of the cache line granted during such arbitration until modification of the data is complete. The data processing system includes a plurality of agents coupled to an interconnect that supports pipelined transactions. While data associated with a target address are cached at a first agent among the plurality of agents in a shared state, the first agent issues a transaction on the interconnect. In response to snooping the transaction, a second agent provides a snoop response indicating that the second agent has a pending conflicting request and a coherency decision point provides a snoop response granting the first agent ownership of the data. In response to the snoop responses, the first agent is provided with a combined response representing a collective response to the transaction of all of the agents that grants the first agent ownership of the data. In response to the combined response, the first agent is permitted to modify the data.
摘要翻译： 这里公开了一种数据处理系统和方法，该数据处理系统和方法在数据处理系统之间进行仲裁，以便在冲突的请求之间进行仲裁，以修改在共享状态下缓存的数据，并保护在此类仲裁期间授予的高速缓存行的所有权，直到数据修改完成。 数据处理系统包括耦合到支持流水线交易的互连的多个代理。 虽然与目标地址相关联的数据在共享状态的多个代理之间的第一代理处被高速缓存，但第一代理在互连上发布事务。 响应于窥探事务，第二代理提供窥探响应，指示第二代理具有待决冲突请求，并且一致性决策点提供准备数据的第一代理所有权的窥探响应。 响应于窥探响应，向第一代理提供组合的响应，其表示对授予数据的第一代理所有权的所有代理的交易的集体响应。 响应于组合的响应，允许第一代理修改数据。
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公开(公告)号：US06691220B1
公开(公告)日：2004-02-10
申请号：US09588608
申请日：2000-06-06
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3859
摘要： A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.
摘要翻译： 一种处理器内的操作方法，其允许按照指令序列中的障碍指令之后的加载指令进行推测。 屏障指令被执行，并且当屏障操作正在等待时，推测地发出与加载指令相关联的加载请求。 设置了一个猜测标志来指示加载指令被推测发出。 当接收到屏障操作的确认时，该标志被复位。 在接收到确认之前返回的数据被暂时保留，并且仅在接收到确认之后将数据转发到处理器的寄存器和/或执行单元。 如果在屏障操作完成之前，对于推测发出的负载请求检测到窥探无效，则丢弃数据并重新发出加载请求。
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