公开(公告)号：US20100155896A1

公开(公告)日：2010-06-24

申请号：US12716692

申请日：2010-03-03

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L29/73

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US07371650B2

公开(公告)日：2008-05-13

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

Inventor： Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US07135757B2

公开(公告)日：2006-11-14

申请号：US10912344

申请日：2004-08-04

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L27/082

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US20060171116A1

公开(公告)日：2006-08-03

申请号：US11324789

申请日：2006-01-03

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schafer

IPC: H05K7/20

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US07064360B2

公开(公告)日：2006-06-20

申请号：US10470816

申请日：2002-02-04

Applicant: Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Franosch ,  Thomas Meister ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the base width (low temperature budget). The temperature budget can be kept low in the base region since no implantations are required in order to reduce the base connection resistance. Furthermore, the difficulties associated with the point defects are largely avoided.

Abstract translation: 提供了一种制造具有低基极连接电阻，低缺陷密度和改进的可扩展性的双极晶体管的方法。 在这种情况下可以理解可扩展性，因为发射器窗口的横向缩放和基础宽度（低温预算）的垂直缩放。 由于不需要植入来降低基极连接电阻，所以在基极区域中的温度预算可以保持较低。 此外，很大程度上避免了与点缺陷相关的困难。

公开(公告)号：US20060040456A1

公开(公告)日：2006-02-23

申请号：US11240297

申请日：2005-09-30

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar semiconductor element, especially a bipolar transistor, and a corresponding bipolar semiconductor component. The inventive method comprises the following steps: a first semiconductor area (32, 34) of a first conductivity type (p) is provided above a semiconductor substrate (1); a connecting area (40) of the first conductivity type (p ) is provided above the semiconductor area (32, 34); a first insulating area (35″) is provided above the connecting area (40); a window (F) is formed within the first insulating area (35″) and the connecting area (40) so as to at least partly expose the semiconductor area (32, 34); a sidewall spacer (80) is provided in the window (F) in order to insulate the connecting area (40); a second semiconductor area (60) of the second conductivity type (n+) is provided so as to cover the sidewall spacer (80) and a portion of the surrounding first insulating area (35″); the surrounding first insulating area (35″) and the sidewall spacer (80) are removed in order to form a gap (LS) between the connecting area (40) and the second semiconductor area (60); and the gap (LS) is sealed by means of a second insulating area (100) while a gaseous atmosphere or a vacuum atmosphere is provided inside the sealed gap (LS).

Abstract translation: 本发明涉及一种用于制造双极型半导体元件，特别是双极晶体管的方法和相应的双极半导体元件。 本发明的方法包括以下步骤：第一导电类型（p）的第一半导体区域（32,34）设置在半导体衬底（1）的上方; 在半导体区域（32,34）的上方设置第一导电类型（p +）的连接区域（40）。 第一绝缘区域（35“）设置在连接区域40上方; 在第一绝缘区域（35“）和连接区域（40）内形成窗口（F），以便至少部分地暴露半导体区域（32,34）; 在窗口（F）中设置侧壁间隔件（80）以使连接区域（40）绝缘; 提供第二导电类型（n +）的第二半导体区域（60），以覆盖侧壁间隔物（80）和周围的第一绝缘区域（35“）的一部分; 为了在连接区域（40）和第二半导体区域（60）之间形成间隙（LS），除去周围的第一绝缘区域（35“）和侧壁间隔物（80） 并且在所述密封间隙（LS）的内部设置有气氛或真空气氛的同时，所述间隙（LS）借助于第二绝缘区域（100）密封。

公开(公告)号：US20060009002A1

公开(公告)日：2006-01-12

申请号：US10532894

申请日：2003-10-24

Applicant: Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

Inventor： Josef Bock ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer ,  Martin Seck

IPC: H01L21/331 ,  H01L21/8228

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US06635545B2

公开(公告)日：2003-10-21

申请号：US10160630

申请日：2002-06-03

Applicant: Josef Böck ,  Wolfgang Klein ,  Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Reinhard Stengl

Inventor： Josef Böck ,  Wolfgang Klein ,  Herbert Schäfer ,  Martin Franosch ,  Thomas Meister ,  Reinhard Stengl

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

公开(公告)号：US06469887B2

公开(公告)日：2002-10-22

申请号：US10011133

申请日：2001-11-13

Applicant: Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

Inventor： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

IPC: H01G406

CPC classification number: H01L27/1085 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

公开(公告)号：US06468348B1

公开(公告)日：2002-10-22

申请号：US09539237

申请日：2000-03-30

Applicant: Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

Inventor： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

IPC: C30B2504

CPC classification number: B32B38/10 ,  B82Y20/00 ,  C30B25/00 ,  C30B29/60 ,  G02B6/1225

Abstract: An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.

Abstract translation: 在每种情况下制造具有多个二维结构化层的开放形式。 该形式由根据其掺杂可蚀刻的硅制成。 首先制造第一硅层，并且通过掺杂第一层的至少一个区域来标记属于待生产形式的第一层的一部分。 随后，施加至少一个另外的硅层，并且还在其中标记属于该形式的部分。 最后，根据各层的相应掺杂，通过蚀刻去除层的每个未标记部分。 开放形式尤其是光子晶体。