公开(公告)号：US08084759B2

公开(公告)日：2011-12-27

申请号：US11931449

申请日：2007-10-31

申请人： Ulrich Klostermann ,  Ulrike Grüning-von Schwerin ,  Franz Kreupl

发明人： Ulrich Klostermann ,  Ulrike Grüning-von Schwerin ,  Franz Kreupl

IPC分类号： H01L29/02

CPC分类号： H01L27/228 ,  H01L21/743 ,  H01L21/76224 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06

摘要： An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

摘要翻译： 集成电路包括形成在半导体衬底中的存储单元阵列和掺杂半导体线。 掺杂半导体线耦合到一行存储器单元。 集成电路包括与掺杂半导体线接触的导电包层。

公开(公告)号：US07125778B2

公开(公告)日：2006-10-24

申请号：US10228886

申请日：2002-08-27

申请人： Dirk Efferenn ,  Ulrike Grüning Von Schwerin ,  Hans-Peter Moll ,  Jörg Radecker ,  Andreas Wich-Glasen

发明人： Dirk Efferenn ,  Ulrike Grüning Von Schwerin ,  Hans-Peter Moll ,  Jörg Radecker ,  Andreas Wich-Glasen

IPC分类号： H01L21/336

CPC分类号： H01L21/0337

摘要： A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

公开(公告)号：US06468348B1

公开(公告)日：2002-10-22

申请号：US09539237

申请日：2000-03-30

申请人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

发明人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

IPC分类号： C30B2504

CPC分类号： B32B38/10 ,  B82Y20/00 ,  C30B25/00 ,  C30B29/60 ,  G02B6/1225

摘要： An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.

摘要翻译： 在每种情况下制造具有多个二维结构化层的开放形式。 该形式由根据其掺杂可蚀刻的硅制成。 首先制造第一硅层，并且通过掺杂第一层的至少一个区域来标记属于待生产形式的第一层的一部分。 随后，施加至少一个另外的硅层，并且还在其中标记属于该形式的部分。 最后，根据各层的相应掺杂，通过蚀刻去除层的每个未标记部分。 开放形式尤其是光子晶体。

公开(公告)号：US06194765B1

公开(公告)日：2001-02-27

申请号：US09313433

申请日：1999-05-17

申请人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

发明人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

摘要翻译： 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

公开(公告)号：US07279742B2

公开(公告)日：2007-10-09

申请号：US11024935

申请日：2004-12-30

申请人： Ulrike Grüning-Von Schwerin

发明人： Ulrike Grüning-Von Schwerin

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66795 ,  H01L29/785

摘要： A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length Leff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width Weff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

摘要翻译： 具有沿着x轴布置在水平面中的源极/漏极区域的晶体管结构具有凹陷结构，其将两个源极/漏极区彼此分离并且增加了源极/漏极区域的有效沟道长度L eff 晶体管结构。 相对于水平面的垂直栅极电极沿x轴延伸，并且在这种情况下，从两侧或完全封闭晶体管结构的有源区。 有效沟道宽度W eff取决于形成栅电极的深度。 具有根据晶体管结构的选择晶体管的存储单元具有低漏电流和良好的开关行为。 通过合适的集成概念，晶体管结构集成到具有空穴沟槽电容器或堆叠电容器的DRAM的存储单元阵列中。

公开(公告)号：US06828192B2

公开(公告)日：2004-12-07

申请号：US10657928

申请日：2003-09-10

申请人： Wolfgang Gustin ,  Ulrike Grüning-Von Schwerin ,  Dietmar Temmler ,  Martin Schrems ,  Stefan Rongen ,  Rudolf Strasser

发明人： Wolfgang Gustin ,  Ulrike Grüning-Von Schwerin ,  Dietmar Temmler ,  Martin Schrems ,  Stefan Rongen ,  Rudolf Strasser

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L27/10873

摘要： A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

摘要翻译： 在沟槽中形成沟槽电容器，其设置在基板中。 沟槽填充有用作内部电容器电极的导电沟槽填充物。 在衬底上的沟槽的侧壁上生长外延层。 掩埋带设置在填充有第二中间层的导电沟槽和外延生长层之间。 在外延生长层中设置从掩埋带形成的掺杂剂外扩散。 通过外延生长层，从布置在沟槽旁边的选择晶体管进一步去除掺杂剂扩散，结果可以避免选择晶体管中的短沟道效应。

公开(公告)号：US06614575B1

公开(公告)日：2003-09-02

申请号：US09636521

申请日：2000-08-10

申请人： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

发明人： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

IPC分类号： G02F103

CPC分类号： B82Y20/00 ,  G02B6/1225

摘要： An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

摘要翻译： 光学结构包括具有半导体材料和光栅结构的衬底。 光栅结构具有发射至少一个频带的特性，使得具有来自该频带的频率的光不能在光栅结构中传播。 光栅结构具有孔和缺陷区的构造。 孔以周期性阵列设置在缺陷区域的外侧，并且周期性阵列在缺陷区域中受到干扰。 光栅结构的表面至少在缺陷区域附近设置有导电层。 还提供了一种用于制造光学结构的方法。

公开(公告)号：US07301192B2

公开(公告)日：2007-11-27

申请号：US11222273

申请日：2005-09-08

申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。