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    Optical structure and method for producing the same
    1.
    发明授权
    Optical structure and method for producing the same 有权
    光学结构及其制造方法

    公开(公告)号：US06614575B1

    公开(公告)日：2003-09-02

    申请号：US09636521

    申请日：2000-08-10

    申请人： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

    发明人： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

    IPC分类号： G02F103

    CPC分类号： B82Y20/00 ,  G02B6/1225

    摘要： An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

    摘要翻译： 光学结构包括具有半导体材料和光栅结构的衬底。 光栅结构具有发射至少一个频带的特性，使得具有来自该频带的频率的光不能在光栅结构中传播。 光栅结构具有孔和缺陷区的构造。 孔以周期性阵列设置在缺陷区域的外侧，并且周期性阵列在缺陷区域中受到干扰。 光栅结构的表面至少在缺陷区域附近设置有导电层。 还提供了一种用于制造光学结构的方法。

    Method of producing an open form
    2.
    发明授权
    Method of producing an open form 有权
    打开形式的制作方法

    公开(公告)号：US06468348B1

    公开(公告)日：2002-10-22

    申请号：US09539237

    申请日：2000-03-30

    申请人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

    发明人： Ulrike Grüning ,  Hermann Wendt ,  Volker Lehmann ,  Reinhard Stengl ,  Hans Reisinger

    IPC分类号： C30B2504

    CPC分类号： B32B38/10 ,  B82Y20/00 ,  C30B25/00 ,  C30B29/60 ,  G02B6/1225

    摘要： An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.

    摘要翻译： 在每种情况下制造具有多个二维结构化层的开放形式。 该形式由根据其掺杂可蚀刻的硅制成。 首先制造第一硅层，并且通过掺杂第一层的至少一个区域来标记属于待生产形式的第一层的一部分。 随后，施加至少一个另外的硅层，并且还在其中标记属于该形式的部分。 最后，根据各层的相应掺杂，通过蚀刻去除层的每个未标记部分。 开放形式尤其是光子晶体。

    Integrated electrical circuit having at least one memory cell and method for fabricating it
    3.
    发明授权
    Integrated electrical circuit having at least one memory cell and method for fabricating it 有权
    具有至少一个存储单元的集成电路及其制造方法

    公开(公告)号：US06194765B1

    公开(公告)日：2001-02-27

    申请号：US09313433

    申请日：1999-05-17

    申请人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

    发明人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

    摘要翻译： 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

    Method for fabricating a capacitor for a semiconductor memory configuration
    6.
    发明授权
    Method for fabricating a capacitor for a semiconductor memory configuration 有权
    制造半导体存储器配置的电容器的方法

    公开(公告)号：US6117790A

    公开(公告)日：2000-09-12

    申请号：US302655

    申请日：1999-04-30

    申请人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

    发明人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

    摘要： A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

    摘要翻译： 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。

    Electrically programmable non-volatile memory cell configuration
    7.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L2972

    CPC分类号： H01L21/8229 ,  H01L27/1021

    摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Method for fabricating a dopant region
    8.
    发明授权
    Method for fabricating a dopant region 有权
    掺杂剂区域的制造方法

    公开(公告)号：US6133126A

    公开(公告)日：2000-10-17

    申请号：US398688

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

    CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

    摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

    摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

    Method of operating a storage cell arrangement
    10.
    发明授权
    Method of operating a storage cell arrangement 失效
    操作存储单元布置的方法

    公开(公告)号：US6040995A

    公开(公告)日：2000-03-21

    申请号：US230614

    申请日：1999-01-28

    申请人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    发明人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    IPC分类号： H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

    CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

    摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。