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145 条记录 (耗时 0.046 秒)

    Stepper alignment mark structure for maintaining alignment integrity
    51.
    发明授权
    Stepper alignment mark structure for maintaining alignment integrity 有权
    用于保持对准完整性的步进对准标记结构

    公开(公告)号：US6037671A

    公开(公告)日：2000-03-14

    申请号：US184861

    申请日：1998-11-03

    申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： G03F9/00 ,  H01L23/544

    CPC分类号： G03F9/7076 ,  G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

    摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

    摘要翻译： 使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本上透明的层。 实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。 分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。 由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

    Shallow trench isolation formation with improved trench edge oxide
    52.
    发明授权
    Shallow trench isolation formation with improved trench edge oxide 失效
    浅沟槽隔离形成，具有改善的沟槽边缘氧化物

    公开(公告)号：US5970363A

    公开(公告)日：1999-10-19

    申请号：US993827

    申请日：1997-12-18

    申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

    IPC分类号： H01L21/762 ,  H01L21/8242

    CPC分类号： H01L21/76232

    摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.

    摘要翻译： 形成浅沟槽隔离结构，其能够在沟槽边缘处生长高质量的栅极氧化物。 实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。 在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上。 然后抛光停止层被掩蔽到沟槽边缘，并且沟槽中的抛光停止被蚀刻掉。 然后用绝缘材料填充沟槽，将绝缘材料平坦化，并通过蚀刻去除抛光止动件。 因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。 此外，沟槽中不留下抛光停止层，引起不必要的电气效应。

    Immersion lithographic process using a conforming immersion medium
    56.
    发明授权
    Immersion lithographic process using a conforming immersion medium 失效
    浸渍光刻工艺使用一致的浸渍介质

    公开(公告)号：US07125652B2

    公开(公告)日：2006-10-24

    申请号：US10726413

    申请日：2003-12-03

    申请人： Christopher F. Lyons ,  Carl P. Babcock ,  Jongwook Kye

    发明人： Christopher F. Lyons ,  Carl P. Babcock ,  Jongwook Kye

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70341

    摘要： A method of making a device using a lithographic system having a lens from which an exposure pattern is emitted. A conforming immersion medium can be positioned between a photo resist layer and the lens. The photo resist layer, which can be disposed over a wafer, and the lens can be brought into intimate contact with the conforming immersion medium. The photo resist can then be exposed with the exposure pattern so that the exposure pattern traverses the conforming immersion medium.

    摘要翻译： 一种制造使用具有透镜的光刻系统的装置的方法，曝光图案从该透镜发射。 适配浸没介质可以位于光致抗蚀剂层和透镜之间。 可以设置在晶片上的光致抗蚀剂层，并且透镜可以与合适的浸渍介质紧密接触。 然后可以用曝光图案曝光光致抗蚀剂，使得曝光图案穿过合适的浸渍介质。

    Shallow trench isolation polish stop layer for reduced topography
    57.
    发明授权
    Shallow trench isolation polish stop layer for reduced topography 失效
    浅沟隔离抛光停止层减少地形

    公开(公告)号：US07056804B1

    公开(公告)日：2006-06-06

    申请号：US10790366

    申请日：2004-03-01

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A method of making and shallow trench isolation feature including 1) providing a semiconductor substrate, 2) forming a polish stop layer over the semiconductor substrate, 3) forming a nitride containing layer over the polish stop layer, 4) forming a shallow trench layer through a portion of the nitride containing layer, a portion of the polish stop layer and a portion of the semiconductor substrate, 5) removing the nitride containing layer by a chemical mechanical polishing process, and 6) planarizing the shallow trench layer and the polish stop layer until a surface of the shallow trench layer and a surface of the polish stop layer are co-planar.

    摘要翻译： 一种制造和浅沟槽隔离特征的方法，包括1）提供半导体衬底，2）在半导体衬底上形成抛光停止层，3）在抛光停止层上形成含氮化物层，4）形成浅沟槽层， 含氮化物层的一部分，抛光停止层的一部分和半导体衬底的一部分，5）通过化学机械抛光工艺除去含氮化物层，以及6）使浅沟槽层和抛光停止层平坦化 直到浅沟槽层的表面和抛光停止层的表面是共面的。

    Metal bridging monitor for etch and CMP endpoint detection
    59.
    发明授权
    Metal bridging monitor for etch and CMP endpoint detection 失效
    用于蚀刻和CMP端点检测的金属桥接监视器

    公开(公告)号：US07011762B1

    公开(公告)日：2006-03-14

    申请号：US10419534

    申请日：2003-04-21

    申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Steven C. Avanzino

    IPC分类号： C23F1/00 ,  G01R31/00

    CPC分类号： H01L21/3212 ,  H01L21/32051 ,  H01L21/32136 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.

    摘要翻译： 本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测 当它通过减色金属化过程进行时。 本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。 该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动 从电传感器检测和接收，用于实时监测减色金属化处理。

    Ion implantation to modulate amorphous carbon stress
    60.
    发明授权
    Ion implantation to modulate amorphous carbon stress 失效
    离子注入调节无定形碳应力

    公开(公告)号：US06989332B1

    公开(公告)日：2006-01-24

    申请号：US10217730

    申请日：2002-08-13

    申请人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    发明人： Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Christopher F. Lyons

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  C23C16/26 ,  C23C16/56 ,  H01L21/0332

    摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.

    摘要翻译： 一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。 在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。 将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。