公开(公告)号：US20060202245A1

公开(公告)日：2006-09-14

申请号：US11337787

申请日：2006-01-23

Applicant: Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

Inventor： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

IPC: H01L29/94

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

Abstract translation: 一种相变存储器件，其中存储器单元形成以行和列布置的存储器阵列。 存储单元由连接到选择装置的MOS选择装置和相变区域形成。 选择装置由在半导体衬底中延伸并且经由沟道区彼此间隔开的第一和第二导电区域以及连接到相应行并且覆盖沟道区域的隔离控制区域形成。 第一导电区域连接到与行平行延伸的连接线，第二导电区域连接到相变区域，并且相变区域连接到相应的列。 第一连接线是金属互连线，并且通过作为点接触而不同于第一连接线的源极接触区域连接到第一导电区域。

公开(公告)号：US06972430B2

公开(公告)日：2005-12-06

申请号：US10371154

申请日：2003-02-20

Applicant: Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

Inventor： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC: G11C11/56 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract translation: 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US06891747B2

公开(公告)日：2005-05-10

申请号：US10372761

申请日：2003-02-20

Applicant: Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

Inventor： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC: G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G11C11/00

CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

Abstract translation: 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US06750505B2

公开(公告)日：2004-06-15

申请号：US10337556

申请日：2003-01-07

Applicant: Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract translation: 用于在半导体衬底上制造非易失性存储单元的工艺包括由氧化物层形成由与衬底隔离的第一多晶硅层组成的堆叠结构。 级联蚀刻第一多晶硅层，氧化物层和半导体衬底以限定电池的浮动栅极区域的第一部分和与存储器单元的有效区域接合的至少一个沟槽。 至少一个沟槽填充有隔离层。 该方法还包括在半导体的整个暴露表面上沉积第二多晶硅层，以及蚀刻第二多晶硅层以暴露形成在第一多晶硅层中的浮栅区域，从而形成与第一多晶硅层的上述部分相邻的延伸。

公开(公告)号：US06567296B1

公开(公告)日：2003-05-20

申请号：US10041684

申请日：2001-10-24

Applicant: Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

Inventor： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

IPC: G11C1706

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

Abstract: A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

Abstract translation: 一种存储器件，包括多个存储器单元，形成在半导体材料的芯片中的第一类型的导电性的多个绝缘的第一区域，在每个第一区域中形成的至少一个第二导电类型的第二区域， 每个第二区域和相应的第一区域限定单向传导访问元件，用于当正向偏置时选择连接到第二区域的对应的存储单元，以及用于接触每个第一区域的至少一个触点; 在每个第一区域中形成多个访问元件，所述访问元件被分组成由多个相邻的访问元件组成的至少一个子集，而不插入任何联系人，并且所述存储器设备还包括： 每个子集的元素同时进行。

公开(公告)号：US06294431B1

公开(公告)日：2001-09-25

申请号：US09547520

申请日：2000-04-12

Applicant: Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

Inventor： Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

IPC: H01L218247

CPC classification number: H01L27/11521

Abstract: A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines. In said step for the definition of the source lines, a process step comprises selectively introducing dopant to form a layer of buried silicon with high concentration of dopant, said layer of buried silicon being formed to such a depth to coincide with the regions of silicon of the underlying field oxide zones, and the introduction of dopant in said active regions of the source lines to superficially contact said layer of buried silicon.

Abstract translation: 一种用于制造具有以矩阵结构的字线和列布置的存储单元的非易失性存储器的过程，其中源极线平行延伸并插入到所述线中，所述源极线由插入到场氧化物区域的有源区形成，所述源极线 过程包括用于定义所述非易失性存储器单元矩阵的所述列的有效区域和所述场氧化物区域的定义的步骤，用于定义所述非易失性存储器单元矩阵的行的后续步骤，以及 以下步骤用于定义所述源线。 在用于定义源极线的所述步骤中，处理步骤包括选择性地引入掺杂剂以形成具有高浓度掺杂剂的掩埋硅层，所述掩埋硅层被形成为与硅的区域重合的深度 底层场氧化物区域，以及在源极线的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层。