公开(公告)号：US07551465B2

公开(公告)日：2009-06-23

申请号：US11741462

申请日：2007-04-27

申请人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

发明人： Tecla Ghilardi ,  Paolo Tessariol ,  Giorgio Servalli ,  Alessandro Grossi ,  Angelo Visconti ,  Emilio Camerlenghi

IPC分类号： G11C5/02 ,  G11C7/02

CPC分类号： G11C16/28

摘要： A reference cell layout includes a plurality of active areas, in parallel to each other, and a first contact of the active areas, and a first gate, the first contact shorting the active areas. A memory device includes the reference cell layout and a corresponding array of memory cells having active areas sized substantially identical to the active areas of the reference cell layout and plural second contacts respectively contacting the active areas of the memory cells.

摘要翻译： 参考单元布局包括彼此并联的多个有效区域和有源区域的第一接触，以及第一栅极，第一接触部使有源区域短路。 存储器件包括参考单元格布局和相应的存储器单元阵列，其存储单元阵列具有大小与参考单元布局的有效区域基本相同的有效区域，以及分别接触存储单元的有效区域的多个第二触点。

公开(公告)号：US06420223B2

公开(公告)日：2002-07-16

申请号：US09730518

申请日：2000-12-05

申请人： Emilio Camerlenghi

发明人： Emilio Camerlenghi

IPC分类号： H01L218238

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11534

摘要： A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix. A self-aligned etching step is performed to define the gate regions of the memory cells, and dopants are implanted in the junction areas to produce the source/drain regions of the memory cells.

摘要翻译： 提供了一种用于在具有包括N沟道和P沟道MOS晶体管的相关控制电路的单元矩阵中形成浮栅非易失性存储单元的过程。 该过程包括在用于单元矩阵和相关联的控制电路的衬底中形成有源区。 第一薄氧化物层和第一多晶硅层沉积在有源区上以产生存储单元的浮动栅区，并且第二介电层沉积在有源区上。 然后将第二多晶硅层沉积在有源区上。 执行掩模和蚀刻步骤，用于暴露相关控制电路的衬底，随后沉积第三多晶硅层。 第三多晶硅层被定义为产生用于相关联的控制电路的晶体管的栅极区域，而第三多晶硅层从单元矩阵中移除。 执行自对准蚀刻步骤以限定存储器单元的栅极区域，并且在结区域中注入掺杂剂以产生存储器单元的源极/漏极区域。

公开(公告)号：US6124169A

公开(公告)日：2000-09-26

申请号：US999403

申请日：1997-12-29

申请人： Emilio Camerlenghi ,  Paolo Caprara ,  Gabriella Fontana

发明人： Emilio Camerlenghi ,  Paolo Caprara ,  Gabriella Fontana

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/76897 ,  H01L21/76838 ,  H01L2924/3011

摘要： A process creates contacts in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure. The cross-point structure includes memory cell matrices in which the bit lines are parallel unbroken diffusion strips extending along a column of the matrix with the contacts being provided through associated contact apertures defined through a dielectric layer deposited over a contact region defined on a semiconductor substrate at one end of the bit lines. The process calls for a step of implantation and following diffusion of contact areas provided in the substrate at opposite sides of each bit line to be contacted to widen the area designed to receive the contacts.

摘要翻译： 一种工艺在半导体电子器件中产生触点，特别是在具有交叉点结构的非易失性存储器的位线上。 交叉点结构包括存储单元矩阵，其中位线是沿着矩阵的列延伸的平行的不间断扩散条，触点通过相关联的接触孔提供，该接触孔通过沉积在限定在半导体衬底上的接触区域上的电介质层 在位线的一端。 该过程需要植入步骤，并且在每个位线的相对侧处设置在衬底中的接触区域扩散以便扩大被设计用于接收触点的区域。

公开(公告)号：US5659516A

公开(公告)日：1997-08-19

申请号：US368211

申请日：1995-01-03

申请人： Giulio Casagrande ,  Emilio Camerlenghi

发明人： Giulio Casagrande ,  Emilio Camerlenghi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。

公开(公告)号：US20070026610A1

公开(公告)日：2007-02-01

申请号：US11457948

申请日：2006-07-17

申请人： Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

发明人： Emilio Camerlenghi ,  Alfonso Maurelli ,  Daniela Peschiaroli ,  Paola Zabberoni

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

摘要： An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions of the first electronic devices. The first protective spacers are defined by first and second sealing layers adjacent one another. Second electronic devices are adjacent the second portion of the semiconductor substrate. Each second electronic device includes a second region comprising a second conductive layer projecting from the semiconductor substrate. Second protective spacers are adjacent sidewalls of the second regions of the second electronic devices. The second protective spacers are defined by other portions of the second sealing layer. The second sealing layer has a thickness less than a thickness of the first sealing layer.

摘要翻译： 集成电路包括包括第一和第二部分的半导体衬底，第一电子器件与第一部分相邻。 每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。 第一保护间隔物是第一电子器件的第一区域的相邻侧壁。 第一保护隔离物由彼此相邻的第一和第二密封层限定。 第二电子器件与半导体衬底的第二部分相邻。 每个第二电子器件包括第二区域，其包括从半导体衬底突出的第二导电层。 第二保护间隔物是第二电子器件的第二区域的相邻侧壁。 第二保护隔离物由第二密封层的其它部分限定。 第二密封层的厚度小于第一密封层的厚度。

公开(公告)号：US06903995B2

公开(公告)日：2005-06-07

申请号：US10449761

申请日：2003-05-30

申请人： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

发明人： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C8/00

CPC分类号： G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

摘要： An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

摘要翻译： 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。

公开(公告)号：US06242793B1

公开(公告)日：2001-06-05

申请号：US09231129

申请日：1998-12-30

申请人： Paolo Colombo ,  Emilio Camerlenghi

发明人： Paolo Colombo ,  Emilio Camerlenghi

IPC分类号： H01L2973

CPC分类号： H01L29/735 ,  H01L27/0259

摘要： A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

公开(公告)号：US5905677A

公开(公告)日：1999-05-18

申请号：US831046

申请日：1997-04-01

申请人： Giulio Casagrande ,  Emilio Camerlenghi

发明人： Giulio Casagrande ,  Emilio Camerlenghi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

摘要翻译： 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。

公开(公告)号：US5682349A

公开(公告)日：1997-10-28

申请号：US454650

申请日：1995-05-31

申请人： Giovanni Campardo ,  Emilio Camerlenghi

发明人： Giovanni Campardo ,  Emilio Camerlenghi

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G11C11/34

CPC分类号： G11C29/82 ,  G11C16/34 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

摘要： Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

摘要翻译： 由于在正常操作期间发生诸如电池增益和电池排空的降低的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障（例如低纹理）的装置（TST），并且写入 用于在与存在于矩阵（MAT）中的冗余行和/或列（RID）对应的正常操作地址期间在所述非易失性存储器（NVM）上写入的装置（WM），以纠正所述故障。

公开(公告)号：US08211762B1

公开(公告)日：2012-07-03

申请号：US12512907

申请日：2009-07-30

申请人： Emilio Camerlenghi ,  Giulio Albini

发明人： Emilio Camerlenghi ,  Giulio Albini

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L27/11521

摘要： Briefly, embodiments of non-volatile memory and embodiments of fabrication thereof are disclosed. For example, a non-volatile memory device having a gate assembly with a floating gate and a control gate assembly is described. The control gate assembly includes a non-metal conductive control gate and a metal control gate in one embodiment. Additional embodiments are described, including use of a sacrificial nitride layer and forming contact recesses to create source or drain contacts, as other examples.

摘要翻译： 简而言之，公开了非易失性存储器的实施例及其制造的实施例。 例如，描述了具有带有浮动栅极和控制栅极组件的栅极组件的非易失性存储器件。 在一个实施例中，控制门组件包括非金属导电控制栅极和金属控制栅极。 描述了另外的实施例，包括使用牺牲氮化物层和形成接触凹部来产生源极或漏极接触，如其他示例。