公开(公告)号：USRE36027E

公开(公告)日：1999-01-05

申请号：US664081

申请日：1996-06-13

申请人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

发明人： Kazutami Arimoto ,  Kazuyasu Fujishima ,  Hideto Hidaka ,  Masaki Tsukude ,  Tsukasa Ohishi

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/41 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/1048

摘要： In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of V.sub.CC -V.sub.th, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of 1/2.multidot.V.sub.CC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.

摘要翻译： 在CSL系统的动态RAM中，存储器阵列被分成多个存储器阵列部分，并且设置在各个存储器阵列部分中的位线对响应于CSL输出而同时连接到它们对应的I / O线对 。 在这样的RAM中，只有要访问的存储器阵列部分的I / O线对被预充电到VCC-Vth的电平，而不存储阵列部分的I / O线对被预充电到 + E，fra 1/2 + EE xVCC的电平与位线对相同。 这使得可以实现更快的数据读取操作，并且还防止不必要的电流在未加工的存储器阵列部分中的位线对和I / O线对之间流动。

公开(公告)号：US5856951A

公开(公告)日：1999-01-05

申请号：US864756

申请日：1997-05-29

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/147

摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.

摘要翻译： 在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路 线。 虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。 电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者 二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

公开(公告)号：US5825705A

公开(公告)日：1998-10-20

申请号：US839834

申请日：1997-04-17

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/403 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/402

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C5/147

摘要： A timing generating circuit generates a signal SRE defining a period in which a self-refreshing operation is carried out based on a signal extRAS and a signal extCAS. An internal voltage down-converting circuit controls the level of an internal power supply voltage intVcc to be generated in the period defined by the signal SRE lower in the self-refreshing operation than in a normal operation. As a result, a semiconductor memory device is obtained which reduces current consumption in the self-refreshing operation by simple control in an internal circuit.

公开(公告)号：US5812490A

公开(公告)日：1998-09-22

申请号：US912200

申请日：1997-08-18

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051

摘要： An external clock signal ext.CLK applied to an external clock input pad is transferred to two internal clock generation circuits independent from each other through two independent input first stage circuits. An internal clock signal int.CLK1 controlling the operations of row related circuits and column related circuits is supplied by a first clock generation circuit and an internal clock signal int.CLK2 controlling an output buffer circuit is supplied from a second clock generation circuit.

摘要翻译： 施加到外部时钟输入焊盘的外部时钟信号ext.CLK通过两个独立的输入第一级电路彼此独立地传送到两个内部时钟产生电路。 控制行相关电路和列相关电路的操作的内部时钟信号int.CLK1由第一时钟产生电路提供，并且控制输出缓冲器电路的内部时钟信号int.CLK2由第二时钟发生电路提供。

公开(公告)号：US5703522A

公开(公告)日：1997-12-30

申请号：US708429

申请日：1996-09-05

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： H01L27/02 ,  H01L27/12 ,  H03K19/00 ,  G05F3/16 ,  H03K17/16

CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

摘要： A semiconductor circuit or a MOS-DRAM wherein a converter is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converter includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了一种转换器，其在MOS-DRAM的逻辑电路，存储单元和操作电路中的MOS-FET的两个值之间转换衬底电位或体偏置电位，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换器包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

公开(公告)号：US5666315A

公开(公告)日：1997-09-09

申请号：US576351

申请日：1995-12-21

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/83

摘要： In a reading/writing operation, a bit line pair group including a defective memory cell is replaced with a spare bit line pair group. Supply of a precharge potential to a bit line equalize circuit and a power supply interconnection of a sense amplifier is effected by an interconnection V.sub.BLn connected to ground for every bit line pair group. In the replacement of the bit line pair group, supply of a precharge potential to the bit line pair group is cut by a fuse element.

摘要翻译： 在读/写操作中，包括有缺陷存储单元的位线对组被替换为备用位线对组。 为位线均衡电路提供预充电电位和读出放大器的电源互连由每个位线对组连接到地的互连VBLn实现。 在替换位线对组时，通过熔丝元件向位线对组提供预充电电位。

公开(公告)号：US5267214A

公开(公告)日：1993-11-30

申请号：US616264

申请日：1990-11-20

申请人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

发明人： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Tsukasa Ooishi ,  Masaki Tsukude

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/34

CPC分类号： G11C11/4091 ,  G11C11/4076

摘要： A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to a switching unit for connecting the selected memory block to the sense amplifiers up to a level higher than a power supply voltage Vcc during the activation of the sense amplifiers, and a circuit for separating a memory block paired with the selected memory block from the activated sense amplifiers during the sensing operation. The memory further comprises a circuit for generating a control signal of the power supply voltage Vcc and connecting all the memory blocks to the corresponding sense amplifiers in a stand-by state wherein a row address strobe signal is inactive. With this arrangement, a highly reliable memory consuming less power can be achieved which ensures data writing and/or rewriting at a full Vcc level.

摘要翻译： 动态随机存取存储器放大器装置包括在两个不同存储块之间共享的读出放大器带。 在该存储器中，只有与所选存储器块相关的读出放大器被激活。 存储器包括用于将控制信号电压升压到开关单元的电路，用于在感测放大器的激活期间将选择的存储块连接到读出放大器，直到高于电源电压Vcc的电平，以及用于分离 存储块在感测操作期间与所激活的读出放大器与选择的存储块配对。 存储器还包括用于产生电源电压Vcc的控制信号的电路，并且在行地址选通信号无效的待机状态下将所有存储块连接到相应的读出放大器。 通过这种布置，可以实现消耗更少功率的高度可靠的存储器，其确保在完全Vcc级别的数据写入和/或重写。

公开(公告)号：US4977542A

公开(公告)日：1990-12-11

申请号：US400898

申请日：1989-08-30

申请人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14

CPC分类号： G11C7/14 ,  G11C7/18 ,  G11C8/14

摘要： An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

摘要翻译： 一种用于在包括扭转位线的存储器结构中提供字线和位线之间的电容耦合补偿的装置。 保持在预定电位的两个虚拟字线形成在一对位线的扭转部分。 在虚拟字线和位线的相应扭转部分设置虚拟单元。 在与位线相交的方向上形成多个字线，并且根据位线对的扭绞部分的位置将字线分成四个字线组。 当选择任意字线时，与所选字线所属的字线组对应的至少一个虚拟字线的电位降低。 因此，通过降低至少一个虚拟字线的电位来补偿由字线的选择引起的位线的电位的上升，使得可以减少读取中的误差。 特殊的单元层布置简化了虚拟单元补偿与电容耦合的扭转位线平衡组合的集成密度的增加。

公开(公告)号：US20110199844A1

公开(公告)日：2011-08-18

申请号：US13081821

申请日：2011-04-07

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

IPC分类号： G11C8/18 ,  G11C7/06

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal. the control is also performed in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access

摘要翻译： 公开了一种与时钟同步操作的半导体存储器件。 半导体包括具有以行和列排列的多个存储单元的存储器阵列; 以及控制电路，执行控制，对所选择的行进行行访问处理的操作，并对列执行列访问处理。 该控制与根据外部施加的控制信号的读取信号或写入信号的产生时间所限定的第一时钟同步执行。 控制还与由等待时间定义的第二或更迟的时钟同步地执行，以对在突发模式存取中剩余的第二数量的列进行列访问处理

公开(公告)号：US07983103B2

公开(公告)日：2011-07-19

申请号：US12333913

申请日：2008-12-12

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

摘要翻译： 触发产生电路提供触发信号。 延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。 时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。 确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。 延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。