公开(公告)号：US20230132059A1

公开(公告)日：2023-04-27

申请号：US17915673

申请日：2021-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

IPC: H10K39/32 ,  G06F7/523 ,  G06F7/50

Abstract: A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug. Note that the first to fourth wirings are parallel to each other, and the distance between the third wiring and the fourth wiring is greater than or equal to 0.9 times and less than or equal to 1.1 times the distance between the first wiring and the second wiring.

公开(公告)号：US20230040508A1

公开(公告)日：2023-02-09

申请号：US17788050

申请日：2020-12-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Masashi OOTA ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G06N3/02 ,  H01L29/423 ,  H01L27/105

Abstract: To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

公开(公告)号：US20230004704A1

公开(公告)日：2023-01-05

申请号：US17846110

申请日：2022-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Minato ITO ,  Yusuke KOUMURA ,  Tatsuya ONUKI

IPC: G06F30/392

Abstract: The circuit layout generation system includes a memory portion, a limitation data arithmetic portion, and a layout data arithmetic portion. The memory portion is configured to store circuit connection data and first limitation data. The circuit connection data is data regarding connection of a transistor and a capacitor included in a pixel circuit. The first limitation data includes data that determines a wiring interval of the transistor and a wiring interval of the capacitor and data that determines placement coordinates of the transistor and the capacitor. The limitation data arithmetic portion is configured to generate second limitation data on the basis of the circuit connection data and the first limitation data and store the second limitation data in the memory portion. The second limitation data is data that determines the placement of the transistor and the capacitor designated by the placement coordinates so that the transistor and the capacitor are positioned close to each other. The layout data arithmetic portion is configured to generate layout data on the basis of the circuit connection data, the first limitation data, and the second limitation data.

公开(公告)号：US20220374203A1

公开(公告)日：2022-11-24

申请号：US17769845

申请日：2020-10-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI ,  Takuro KANEMURA

IPC: G06F7/544

Abstract: A semiconductor device that inhibits signal delay and can perform parallel product-sum operations is provided. The semiconductor device includes first to fourth registers, an adder, a multiplier, a selector, and a first memory unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and an output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, and an output terminal of the adder is electrically connected to an input terminal of the third register. An output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register, and the first memory unit is electrically connected to a second input terminal of the multiplier. The first memory unit has a function reading out first data corresponding to a context signal input to the first memory unit and inputting the first data to the second input terminal of the multiplier.

公开(公告)号：US20220276838A1

公开(公告)日：2022-09-01

申请号：US17716239

申请日：2022-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Takeshi AOKI ,  Seiichi YONEDA ,  Yoshiyuki KUROKAWA

IPC: G06F7/544 ,  G06N3/063

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

公开(公告)号：US20220208245A1

公开(公告)日：2022-06-30

申请号：US17604523

申请日：2020-04-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Takayuki IKEDA ,  Kei TAKAHASHI ,  Takeshi AOKI

IPC: G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C11/405 ,  G11C11/4096 ,  G06F3/06

Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.

公开(公告)号：US20200160158A1

公开(公告)日：2020-05-21

申请号：US16604363

申请日：2018-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: G06N3/063 ,  G06F7/57 ,  G06F7/50 ,  G06F7/523

Abstract: A neural network circuit having a novel structure is provided.A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

公开(公告)号：US20200154068A1

公开(公告)日：2020-05-14

申请号：US16715852

申请日：2019-12-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takashi NAKAGAWA ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: H04N5/369 ,  G08B13/196 ,  H04N5/3745 ,  H04N5/232 ,  H01L27/146 ,  H01L27/12 ,  H04N5/343 ,  H04N5/374 ,  H04N5/32 ,  H04N5/376

Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.

公开(公告)号：US20200035726A1

公开(公告)日：2020-01-30

申请号：US16591983

申请日：2019-10-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H01L29/786 ,  H01L31/105 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

公开(公告)号：US20190096206A1

公开(公告)日：2019-03-28

申请号：US16081322

申请日：2017-03-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takashi NAKAGAWA ,  Munehiro KOZUMA ,  Yoshiyuki KUROKAWA ,  Takayuki IKEDA

IPC: G08B13/196 ,  H01L27/146 ,  H04N5/232 ,  H04N5/3745 ,  H04N5/378

Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.