公开(公告)号：US11621222B2

公开(公告)日：2023-04-04

申请号：US17173275

申请日：2021-02-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/66 ,  H01L23/522 ,  H01L21/762 ,  H01L27/08

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US11538941B2

公开(公告)日：2022-12-27

申请号：US17196226

申请日：2021-03-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L29/94 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L27/118

Abstract: An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

公开(公告)号：US11536872B2

公开(公告)日：2022-12-27

申请号：US16450365

申请日：2019-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: H01H37/04 ,  H01H37/32 ,  H01H37/42 ,  H01H9/02 ,  H01L29/423 ,  H01L49/02 ,  G01V7/04 ,  B81B3/00 ,  B81C1/00 ,  H01L21/3213 ,  H01H61/013

Abstract: A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.

公开(公告)号：US11183505B2

公开(公告)日：2021-11-23

申请号：US16939603

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L27/11531 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L27/11521

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

公开(公告)号：US11004785B2

公开(公告)日：2021-05-11

申请号：US16546569

申请日：2019-08-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US10991710B2

公开(公告)日：2021-04-27

申请号：US16391768

申请日：2019-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11565

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US10937746B2

公开(公告)日：2021-03-02

申请号：US16549000

申请日：2019-08-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/08 ,  H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01 ,  H01L27/10

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US10886283B2

公开(公告)日：2021-01-05

申请号：US16525780

申请日：2019-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/11 ,  H01L27/112 ,  H01L23/00 ,  G11C17/18 ,  G11C17/16 ,  H01L23/525

Abstract: An integrated circuit includes at least one antifuse element. The antifuse element is formed from a semiconductor substrate, a trench extending down from a first face of the semiconductor substrate into the semiconductor substrate, a first conductive layer housed in the trench and extending down from the first face of the semiconductor substrate into the semiconductor substrate, a dielectric layer on the first face of the semiconductor substrate, and a second conductive layer on the dielectric layer. A program transistor selectively electrically couples the second conductive layer to a program voltage in response to a program signal. A program/read transistor selectively electrically couples the first conductive layer to a ground voltage in response to the program signal and in response to a read signal. A read transistor selectively electrically couples the second conductive layer to a read amplifier in response to the read signal.

公开(公告)号：US10770357B2

公开(公告)日：2020-09-08

申请号：US16429836

申请日：2019-06-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoit Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L29/06 ,  H01L23/522

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20190310389A1

公开(公告)日：2019-10-10

申请号：US16450365

申请日：2019-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  H01L21/3213 ,  B81C1/00 ,  H01L49/02 ,  B81B3/00 ,  H01H37/32 ,  H01H37/04 ,  H01L29/423

Abstract: A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.