公开(公告)号：US10600479B2

公开(公告)日：2020-03-24

申请号：US16227438

申请日：2018-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfré

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/18 ,  G06F13/16 ,  G06F13/40

Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.

公开(公告)号：US10387334B2

公开(公告)日：2019-08-20

申请号：US15797940

申请日：2017-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Federico Goller ,  Michele Febbrarino

IPC: G06F12/14 ,  G06F13/16 ,  G06F12/02

Abstract: A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.

公开(公告)号：US09978429B2

公开(公告)日：2018-05-22

申请号：US15477695

申请日：2017-04-03

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

公开(公告)号：US20170117051A1

公开(公告)日：2017-04-27

申请号：US15212208

申请日：2016-07-16

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C16/30 ,  G11C16/08

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

公开(公告)号：US09613712B1

公开(公告)日：2017-04-04

申请号：US15212208

申请日：2016-07-16

Applicant: STMicroelectronics S.r.l

Inventor： Fabio Enrico Carlo Disegni ,  Giuseppe Castagna ,  Maurizio Francesco Perroni

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/06 ,  G11C8/10

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.