公开(公告)号：US20070025490A1

公开(公告)日：2007-02-01

申请号：US11191895

申请日：2005-07-28

申请人： Kameran Azadet ,  Fuji Yang

发明人： Kameran Azadet ,  Fuji Yang

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/093 ,  H03L7/0995 ,  H03L2207/50

摘要： Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

摘要翻译： 本发明的实施例包括包括锁相环（PLL）的集成电路。 集成电路包括相位检测器，频率检测器，环路滤波器，数字控制振荡器和相应的多个分频器。 相位检测器基于参考时钟信号与多个时钟相位输入的相位比较来产生第一二进制输出。 频率检测器基于参考时钟信号与时钟相位输入的频率比较产生第二二进制输出。 环路滤波器基于第一个二进制输出和第二个二进制输出产生第三个二进制输出。 基于第三个二进制输出，DCO通过分频器将时钟相位输入反馈到相位检测器，并且基于第三个二进制输出将一个时钟相位反馈到频率检测器。

公开(公告)号：US20060064755A1

公开(公告)日：2006-03-23

申请号：US10945663

申请日：2004-09-21

申请人： Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

发明人： Kameran Azadet ,  Anil Mudichintala ,  Fadi Saibi

IPC分类号： G06F12/14

CPC分类号： H04L63/145 ,  G06F21/564 ,  G06F21/566

摘要： A virus detection mechanism is described in which virus detection is provided by a network integrated protection (NIP) adapter. The NIP adapter checks incoming media data prior to it being activated by a computing device. The NIP adapter operates independently of a host processor to receive information packets from a network. This attribute of independence allows NIP anti-virus (AV) techniques to be “always on” scanning incoming messages and data transfers. By being independent of but closely coupled to the host processor, complex detection techniques, such as using check summing or pattern matching, can be efficiently implemented on the NIP adapter without involving central processor resources and time consuming mass storage accesses. The NIP adapter may be further enhanced with a unique fading memory (FM) facility to allow for a flexible and economical implementation of polymorphic virus detection.

摘要翻译： 描述了病毒检测机制，其中病毒检测由网络集成保护（NIP）适配器提供。 NIP适配器在计算设备激活之前检查传入的媒体数据。 NIP适配器独立于主机处理器操作以从网络接收信息分组。 这种独立性允许NIP防病毒（AV）技术“永远在”扫描传入的消息和数据传输。 通过独立于主机处理器紧密耦合，可以在NIP适配器上有效地实现诸如使用校验和或模式匹配的复杂检测技术，而不涉及中央处理器资源和耗时的大容量存储访问。 NIP适配器可以通过独特的衰落存储器（FM）设施进一步增强，以允许灵活和经济地实施多态性病毒检测。

公开(公告)号：US20050114721A1

公开(公告)日：2005-05-26

申请号：US10874834

申请日：2004-06-23

申请人： Kameran Azadet ,  Leilei Song

发明人： Kameran Azadet ,  Leilei Song

IPC分类号： H02J13/00 ,  H04B1/16 ,  H04B7/26 ,  H04L29/00 ,  H04Q9/00 ,  G06F1/26

CPC分类号： H04W52/0277 ,  Y02D70/142

摘要： A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

摘要翻译： 公开了一种用于电子设备的电源管理的方法和装置。 本发明通过在电池电平降低时通过选择具有降低的功耗的传输模式来降低通过网络进行通信的电子设备的功耗。 公开的电源管理过程监视电子设备的电池电量，并且当电池功率电平达到一个或多个预定阈值电平时，选择具有较低功耗的传输模式（例如，传输速率）。

公开(公告)号：US07913154B2

公开(公告)日：2011-03-22

申请号：US12039474

申请日：2008-02-28

申请人： Kameran Azadet ,  Erich Franz Haratsch

发明人： Kameran Azadet ,  Erich Franz Haratsch

IPC分类号： H03M13/03

CPC分类号： H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

摘要： A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

摘要翻译： 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行）的增加的吞吐量相对于先行深度仅具有线性增加的硬件复杂度。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US20090129519A1

公开(公告)日：2009-05-21

申请号：US12359778

申请日：2009-01-26

申请人： Kameran Azadet ,  Erich Franz Haratsch

发明人： Kameran Azadet ,  Erich Franz Haratsch

IPC分类号： H04L27/06

CPC分类号： H04L25/4923 ,  H04L25/03229 ,  H04L2025/03363

摘要： A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.

摘要翻译： 公开了一种用于联合均衡和解码多级代码的方法和装置，例如在色散信道上传输的MLT-3码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。 超级网格将MLT-3网格与网络格式的通道连接起来。 接收信号的联合均衡和解码可以使用超级格子进行。 公开了一种序列检测器，其使用超级格或相应的缩减状态网格来对接收到的信号进行联合均衡和解码，以解码MLT-3编码的数据位。 可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。

公开(公告)号：US07499498B2

公开(公告)日：2009-03-03

申请号：US11256182

申请日：2005-10-21

申请人： Kameran Azadet ,  Erich Franz Haratsch

发明人： Kameran Azadet ,  Erich Franz Haratsch

IPC分类号： H04L5/12 ,  H04L23/02

CPC分类号： H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

摘要： A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.

摘要翻译： 公开了一种用于改进缩减复杂度序列估计技术（例如缩减状态序列估计（RSSE））的处理时间的方法和装置。 预先计算RSSE中分支度量值的可能值，以允许流水线化和缩短关键路径。 通过分别预先计算多维网格码的每个维度，预先计算的计算负荷被减少用于多维网格码。 使用预滤波技术通过缩短信道存储器来降低计算复杂度。 公开了一种用于具有长度为L的信道存储器的信道的RSSE的混合存活器存储器架构，其中对应于L个过去的解码周期的幸存者被存储在寄存器交换架构中，并且与随后的解码周期相对应的幸存者被存储在跟踪 （TBA）或注册交换架构（REA）。 符号被映射到信息位以在从第一寄存器交换架构移动到追溯架构（TBA）或第二寄存器交换架构之前减小字大小。

公开(公告)号：US07363576B2

公开(公告)日：2008-04-22

申请号：US11234446

申请日：2005-09-26

申请人： Kameran Azadet ,  Erich Franz Haratsch

发明人： Kameran Azadet ,  Erich Franz Haratsch

IPC分类号： H03M13/03

CPC分类号： H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

摘要： A method and apparatus for the implementation of reduced state sequence estimation is disclosed with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

摘要翻译： 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行预测）具有增加的吞吐量，相对于先行深度，硬件复杂度只有线性增加。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US07328227B2

公开(公告)日：2008-02-05

申请号：US11359201

申请日：2006-02-22

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC分类号： G06F7/00

CPC分类号： G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

摘要： An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

摘要翻译： 提供了一种低功率矢量求和装置，用于使用2的补码运算而没有现有技术的高切换活动。 特别地，本发明操作以利用2的补码的符号扩展属性。 提供2的补码减少的表示，以避免符号扩展和符号扩展位的切换。 检测2的补码的最大幅度，并动态生成其缩小表示以表示信号。 通过缩小表示引入的恒定误差也被动态补偿。

公开(公告)号：US20060143259A1

公开(公告)日：2006-06-29

申请号：US11359201

申请日：2006-02-22

申请人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

发明人： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC分类号： G06F7/38

CPC分类号： G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

摘要： An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

公开(公告)号：US20060039492A1

公开(公告)日：2006-02-23

申请号：US11256182

申请日：2005-10-21

申请人： Kameran Azadet ,  Erich Haratsch

发明人： Kameran Azadet ,  Erich Haratsch

IPC分类号： H04L23/02

CPC分类号： H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

摘要： A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.