公开(公告)号：US20210125983A1

公开(公告)日：2021-04-29

申请号：US16946060

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US20200373385A1

公开(公告)日：2020-11-26

申请号：US16821565

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US12288805B2

公开(公告)日：2025-04-29

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US12243874B2

公开(公告)日：2025-03-04

申请号：US18143767

申请日：2023-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Jinbum Kim ,  Haejun Yu ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

公开(公告)号：US12159938B2

公开(公告)日：2024-12-03

申请号：US17711914

申请日：2022-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Sangmoon Lee ,  Jinbum Kim ,  Yongjun Nam

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes; a first fin vertically protruding from a substrate and extending in a first horizontal direction, a second fin vertically protruding from the substrate, an isolation layer contacting side surfaces of the first fin and the second fin, a first lower barrier layer on the first fin, a second lower barrier layer on the second fin, source/drain regions spaced apart in the first horizontal direction on the first lower barrier layer, channel layers disposed between the source/drain regions and vertically spaced apart on the first barrier layer, a gate structure intersecting the first lower barrier layer, surrounding each of the channel layers, and extending in a second horizontal direction, an upper barrier layer on the second lower barrier layer, and first semiconductor layers and second semiconductor layers stacked on the upper barrier layer.

公开(公告)号：US12154988B2

公开(公告)日：2024-11-26

申请号：US17585686

申请日：2022-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

公开(公告)号：US12094974B2

公开(公告)日：2024-09-17

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US12034043B2

公开(公告)日：2024-07-09

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

公开(公告)号：US11996443B2

公开(公告)日：2024-05-28

申请号：US17729676

申请日：2022-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0245 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20240170554A1

公开(公告)日：2024-05-23

申请号：US18511553

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojin Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dongwoo Kim ,  Sungmin Kim ,  Yongjun Nam ,  Ingeon Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in a first direction on a substrate; channel layers arranged on the active pattern; a gate structure crossing the active pattern, and surrounding the plurality of channel layers, the gate structure extending in a second direction that crosses the first direction; and source/drain regions provided on the active pattern on both sides of the gate structure, and including a first epitaxial layer connected to each of side surfaces of the channel layers, and a second epitaxial layer provided on the first epitaxial layer and having a composition different from that of the first epitaxial layer. Each of the side surfaces of the plurality of channel layers has a crystal plane of (111) or (100). The first epitaxial layer extends in the second direction and has a first thickness in the first direction that is substantially constant.