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公开(公告)号:US12094974B2
公开(公告)日:2024-09-17
申请号:US18307279
申请日:2023-04-26
发明人: Jaemun Kim , Dahye Kim , Jinbum Kim , Gyeom Kim , Dohee Kim , Dongwoo Kim , Seunghun Lee
IPC分类号: H01L29/78 , H01L21/8234 , H01L29/417 , H01L29/66 , H01L29/04
CPC分类号: H01L29/785 , H01L21/823431 , H01L29/41791 , H01L29/6681 , H01L29/66818 , H01L29/045
摘要: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.
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公开(公告)号:US11984507B2
公开(公告)日:2024-05-14
申请号:US17206229
申请日:2021-03-19
发明人: Dongwoo Kim , Jinbum Kim , Gyeom Kim , Dohee Kim , Seunghun Lee
IPC分类号: H01L29/78 , H01L21/02 , H01L29/06 , H01L29/161 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号: H01L29/78618 , H01L21/02532 , H01L21/02603 , H01L29/0673 , H01L29/161 , H01L29/41733 , H01L29/42392 , H01L29/66545 , H01L29/66636 , H01L29/66742 , H01L29/78696
摘要: A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.
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公开(公告)号:US11664453B2
公开(公告)日:2023-05-30
申请号:US17192301
申请日:2021-03-04
发明人: Jaemun Kim , Dahye Kim , Jinbum Kim , Gyeom Kim , Dohee Kim , Dongwoo Kim , Seunghun Lee
IPC分类号: H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8234 , H01L29/04
CPC分类号: H01L29/785 , H01L21/823431 , H01L29/41791 , H01L29/6681 , H01L29/66818 , H01L29/045
摘要: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.
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公开(公告)号:US20230076270A1
公开(公告)日:2023-03-09
申请号:US17720880
申请日:2022-04-14
发明人: Dohee Kim , Sunguk Jang , Bongjin Kuh , Kongsoo Lee , Sahwan Hong
IPC分类号: H01L29/06 , H01L27/088 , H01L29/786
摘要: An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.
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公开(公告)号:US12113108B2
公开(公告)日:2024-10-08
申请号:US17472926
申请日:2021-09-13
发明人: Dohee Kim , Gyeom Kim , Jinbum Kim , Haejun Yu , Kyungin Choi , Kihyun Hwang , Seunghun Lee
IPC分类号: H01L29/41 , H01L27/088 , H01L29/417
CPC分类号: H01L29/41775 , H01L27/0886
摘要: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.
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公开(公告)号:US20220246738A1
公开(公告)日:2022-08-04
申请号:US17472926
申请日:2021-09-13
发明人: Dohee Kim , Gyeom Kim , Jinbum Kim , Haejun Yu , Kyungin Choi , Kihyun Hwang , Seunghun Lee
IPC分类号: H01L29/417 , H01L27/088
摘要: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.
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