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公开(公告)号:US12094974B2
公开(公告)日:2024-09-17
申请号:US18307279
申请日:2023-04-26
发明人: Jaemun Kim , Dahye Kim , Jinbum Kim , Gyeom Kim , Dohee Kim , Dongwoo Kim , Seunghun Lee
IPC分类号: H01L29/78 , H01L21/8234 , H01L29/417 , H01L29/66 , H01L29/04
CPC分类号: H01L29/785 , H01L21/823431 , H01L29/41791 , H01L29/6681 , H01L29/66818 , H01L29/045
摘要: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.
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公开(公告)号:US20240170554A1
公开(公告)日:2024-05-23
申请号:US18511553
申请日:2023-11-16
发明人: Hyojin Kim , Jinbum Kim , Sangmoon Lee , Dongwoo Kim , Sungmin Kim , Yongjun Nam , Ingeon Hwang
IPC分类号: H01L29/423 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号: H01L29/42392 , H01L29/0673 , H01L29/0847 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in a first direction on a substrate; channel layers arranged on the active pattern; a gate structure crossing the active pattern, and surrounding the plurality of channel layers, the gate structure extending in a second direction that crosses the first direction; and source/drain regions provided on the active pattern on both sides of the gate structure, and including a first epitaxial layer connected to each of side surfaces of the channel layers, and a second epitaxial layer provided on the first epitaxial layer and having a composition different from that of the first epitaxial layer. Each of the side surfaces of the plurality of channel layers has a crystal plane of (111) or (100). The first epitaxial layer extends in the second direction and has a first thickness in the first direction that is substantially constant.
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公开(公告)号:US20240087884A1
公开(公告)日:2024-03-14
申请号:US18513297
申请日:2023-11-17
发明人: GYEOM KIM , Dongwoo Kim , Jihye Yi , JINBUM KIM , Sangmoon Lee , Seunghun Lee
IPC分类号: H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号: H01L21/02293 , H01L21/28518 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/41791 , H01L29/42392 , H01L29/66439 , H01L29/66553 , H01L29/6656 , H01L29/775 , H01L29/7848 , H01L29/78696
摘要: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.
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公开(公告)号:US11869765B2
公开(公告)日:2024-01-09
申请号:US17853990
申请日:2022-06-30
发明人: Gyeom Kim , Dongwoo Kim , Jihye Yi , Jinbum Kim , Sangmoon Lee , Seunghun Lee
IPC分类号: H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8234 , H01L23/485 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786 , H01L23/532 , B82Y10/00 , H01L29/10 , H01L29/161 , H01L21/28
CPC分类号: H01L21/02293 , H01L21/28518 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/41791 , H01L29/42392 , H01L29/6656 , H01L29/66439 , H01L29/66553 , H01L29/775 , H01L29/7848 , H01L29/78696
摘要: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.
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公开(公告)号:US11419179B2
公开(公告)日:2022-08-16
申请号:US17059560
申请日:2019-06-14
发明人: Jinhong Seol , Jiyong Cho , Dongwoo Kim , Taeseok Lee , Jiho Son , Janghoon Lee
摘要: Various embodiments of the present invention provide a method and apparatus for an emergency call connection by an electronic device. An electronic device according to various embodiments of the present invention may comprise: a first wireless communication circuit for communicating with a first network; a second wireless communication circuit for communicating with a second network; and a processor, wherein the processor: detects a trigger for an emergency call connection; in response to the trigger, initiates the emergency call connection on the basis of the first wireless communication circuit and the second wireless communication circuit; determines priorities of the first and the second wireless communication circuit; and performs the emergency call connection by using a wireless communication circuit determined according to the determined priorities. Various embodiments are possible.
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公开(公告)号:US20220216339A1
公开(公告)日:2022-07-07
申请号:US17467656
申请日:2021-09-07
发明人: Dohyun Lee , Dongwoo Kim , Daeyong Kim , Rakhwan Kim
IPC分类号: H01L29/78 , H01L29/417 , H01L29/10 , H01L29/08 , H01L29/66 , H01L23/522
摘要: The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.
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公开(公告)号:US20210082844A1
公开(公告)日:2021-03-18
申请号:US16848194
申请日:2020-04-14
发明人: Dongwoo Kim , Hyukwoo Kwon , Seongmin Choo , Byoungdeog Choi
IPC分类号: H01L23/00
摘要: An integrated circuit (IC) device includes a lower electrode formed on a substrate, and an upper support structure disposed around the lower electrode and supporting the lower electrode. The upper support structure includes an upper support pattern surrounding the lower electrode and extending in a lateral direction parallel to the substrate, the upper support pattern having a hole through which the lower electrode passes, and an upper spacer support pattern between the upper support pattern and the lower electrode inside the hole and having an outer sidewall in contact with the upper support pattern and an inner sidewall in contact with the lower electrode, wherein a width of the upper spacer support pattern in the lateral direction decreases in a direction toward the substrate. To manufacture an IC device, an upper support pattern is formed on a substrate. An upper spacer support film is formed to cover a sidewall and a top surface of the upper support pattern. A plurality of lower electrodes are formed inside a plurality of holes formed in the upper support pattern. Portions of the upper spacer support film are removed to form a plurality of upper spacer support patterns between the upper support pattern and the lower electrodes, respectively.
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公开(公告)号:US20180261626A1
公开(公告)日:2018-09-13
申请号:US15975861
申请日:2018-05-10
发明人: Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul yoo
IPC分类号: H01L27/11582 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/24 , H01L27/11556 , H01L45/00
CPC分类号: H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.
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公开(公告)号:US20180136713A1
公开(公告)日:2018-05-17
申请号:US15814790
申请日:2017-11-16
发明人: Jaecheol Kim , Jinkyu Kim , Dongwoo Kim , Jeongho Kim , Jaesoo Chaung , Jongshik Ha , Heetae Oh , Hyeokseon Yu , Seungyoung Lee , Wooyoung Choi , Jaewoong Han , Mangun Hur
摘要: An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.
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公开(公告)号:US12080797B2
公开(公告)日:2024-09-03
申请号:US17467656
申请日:2021-09-07
发明人: Dohyun Lee , Dongwoo Kim , Daeyong Kim , Rakhwan Kim
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/66
CPC分类号: H01L29/7851 , H01L29/0847 , H01L29/1033 , H01L29/41791 , H01L29/66553
摘要: The present disclosure provides a semiconductor device. The semiconductor device includes an active region, a plurality of channel layers, gate electrodes, a source/drain region, and a contact structure. The active region is disposed on a substrate and extends in a first direction. The plurality of channel layers are disposed on the active region to be spaced apart from each other vertically. The gate electrodes are disposed on the substrate, intersecting the active region and the plurality of channel layers, extending in a third direction, and surrounding the plurality of channel layers. The source/drain region is disposed on the active region on at least one side of the gate electrodes, and contacting the plurality of channel layers. The contact structure is disposed between the gate electrodes, extending in the second direction, and contacting the source/drain region.
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