公开(公告)号：US06774418B2

公开(公告)日：2004-08-10

申请号：US10303779

申请日：2002-11-25

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L27108

CPC分类号： H01L21/0214 ,  C23C16/308 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76897

摘要： A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.

摘要翻译： 在半导体器件中的栅极叠层上沉积氧氮化硅间隔膜的方法包括使栅叠层与二乙基丁基氨基硅烷（BTBAS），至少一种含氮化合物和氧（O 2）接触。 控制沉积以为沉积的隔离膜提供湿蚀刻速率，其在约25埃/分钟至小于或等于约1埃的范围内。

公开(公告)号：US06744098B2

公开(公告)日：2004-06-01

申请号：US10125979

申请日：2002-04-19

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L2972

CPC分类号： H01L21/0217 ,  C23C16/0218 ,  C23C16/345 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： The invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material. The invention also encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the layer. At least one conductive gate layer is formed over the silicon nitride, and defines a gate layer. A pair of source/drain regions are formed proximate the gate layer and gatedly connected to one another through a channel region that is beneath the gate layer. Additionally, the invention encompasses transistor device structures.

摘要翻译： 本发明包括在含氧化硅的材料上形成氮化硅的方法。 将含氧化硅的材料从含氮等离子体暴露于活性氮物质，以将氮引入材料的上部。 氮在材料内进行热退火，以将氮中的至少一些与接近氮的硅结合。 在退火之后，氮化硅被化学气相沉积在材料的含氮上部上。 本发明还包括形成晶体管器件的方法。 在衬底上形成含氧化硅的层。 将含氧化硅的层从含氮等离子体暴露于氮气以将氮引入层的上部。 氮气在该层内进行热退火以将至少一些氮硅接近氮接合。 在退火之后，氮化硅被化学气相沉积在层的含氮上部上。 在氮化硅上形成至少一个导电栅极层，并且限定栅极层。 在栅极层附近形成一对源极/漏极区，并且通过位于栅极层下方的沟道区相互连接。 另外，本发明包括晶体管器件结构。

公开(公告)号：US06707090B2

公开(公告)日：2004-03-16

申请号：US10393696

申请日：2003-03-20

申请人： Fernando Gonzalez ,  Kevin L. Beaman ,  John T. Moore ,  Ron Weimer

发明人： Fernando Gonzalez ,  Kevin L. Beaman ,  John T. Moore ,  Ron Weimer

IPC分类号： H01L27108

CPC分类号： H01L27/10858 ,  H01L27/1082 ,  H01L27/1203 ,  H01L28/91 ,  Y10S257/906

摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further contains a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

摘要翻译： 本发明包括形成DRAM单元的方法。 第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。 包含单晶材料的第二半导体衬底被结合到第一衬底。 在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。 本发明还包括具有电容器结构的半导体结构以及限定为包围电容器结构的第一衬底。 半导体结构还包含结合到第一衬底和电容器结构上的单晶硅衬底。 另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

公开(公告)号：US06624088B2

公开(公告)日：2003-09-23

申请号：US10118946

申请日：2002-04-10

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L21302

CPC分类号： H01L21/0214 ,  C23C16/308 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76897

摘要： A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.

公开(公告)号：US06528396B2

公开(公告)日：2003-03-04

申请号：US10050631

申请日：2002-01-15

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： The present invention provides an improved surface P-channel transistor and a method of making the same. A preferred embodiment of the method of the present invention includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the method of the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

公开(公告)号：US6096660A

公开(公告)日：2000-08-01

申请号：US915874

申请日：1997-08-21

申请人： David L. Chapek ,  John T. Moore

发明人： David L. Chapek ,  John T. Moore

IPC分类号： H01L21/311 ,  H01L21/314 ,  H01L21/762 ,  H01L21/31 ,  H01L21/76

CPC分类号： H01L21/3144 ,  H01L21/31111 ,  H01L21/76202

摘要： The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.

摘要翻译： 本发明一般涉及在集成电路上去除不理想的第二氧化物，同时最小程度地影响所需的第一氧化物。 集成电路可能是较大系统的一部分。 首先将第二氧化物转化为另一种材料，例如氧氮化物。 另一种材料具有不同的特性，例如蚀刻性质，使得其可被除去，而基本上不会减少第一氧化物。 转化可以通过加热来完成。 加热可以通过快速热处理或炉加工来完成。 随后，例如通过热磷蚀刻从集成电路中除去另一种材料，使得所需的第一氧化物基本上不受影响。

公开(公告)号：US6051480A

公开(公告)日：2000-04-18

申请号：US993329

申请日：1997-12-18

申请人： John T. Moore ,  David L. Chapek

发明人： John T. Moore ,  David L. Chapek

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the non-trench area, similar amounts of material are removed in both the trench area and non-trench area in a subsequent etching process. Consequently, formation of notches and grooves in the semiconductor structure is minimized. A sacrificial oxide layer may be made by depositing a layer of a suitable material on the surface of a semiconductor structure. By depositing a sacrificial oxide layer instead of thermally growing a sacrificial oxide layer, grooves and the notches in the trench areas are filled by the deposited material.

摘要翻译： 在蚀刻沟槽隔离结构中，衬垫氧化物或牺牲氧化物可以形成为与沟槽填料基本上相同（或更高）的蚀刻速率。 因为沟槽区域中的蚀刻速率基本上类似于（或小于）非沟槽区域中的蚀刻速率，所以在随后的蚀刻工艺中，在沟槽区域和非沟槽区域中去除相似量的材料。 因此，半导体结构中的凹口和凹槽的形成最小化。 可以通过在半导体结构的表面上沉积合适的材料层来制造牺牲氧化物层。 通过沉积牺牲氧化物层而不是热生长牺牲氧化物层，沟槽区域中的凹槽和凹口被沉积的材料填充。

公开(公告)号：US4452124A

公开(公告)日：1984-06-05

申请号：US473929

申请日：1983-03-10

申请人： Richard C. Morenus ,  John T. Moore

发明人： Richard C. Morenus ,  John T. Moore

IPC分类号： F41A27/30 ,  F41F3/045 ,  F41F3/04

CPC分类号： F41F3/045 ,  F41A27/30

摘要： A launch tube (2) for launching a missile (4) is supported by a single base (6) which enables the tube (2) to pivot about orthogonal yaw and pitch axes. An aerodynamic stabilizing trim tab (20) is positioned within the interior rear of the launch tube (2). During launch, exhaust gases from the missile (4) flow over the trim tab (20), producing a lift torque which balances the torque about the pitch axis caused by gravity acting upon the missile (4). This gravitational torque would otherwise tend to pull the nose of the launch tube (2) increasingly downward as the missile (4) is launched. The angle of incidence of the trim tab (20), its surface area, and its distance from the pitch axis are varied to adjust the lift torque and the drag attributable to the trim tab (20). The drag is used to balance forward frictional force upon the launch tube (2) caused by the motion of the missile (4). The pitch torques and the linear forces are balanced simultaneously.

摘要翻译： 用于发射导弹（4）的发射管（2）由单个基座（6）支撑，其使得管（2）能够绕正交偏航和俯仰轴线枢转。 气动稳定装饰片（20）位于发射管（2）的内部后部。 在发射期间，来自导弹（4）的废气流过修剪片（20），产生提升力矩，其平衡由作用在导弹（4）上的重力引起的俯仰轴的扭矩。 否则，随着导弹（4）的发射，这种引力将会倾向于使发射管（2）的鼻子越来越下降。 修剪突片（20）的入射角，其表面积和与俯仰轴线的距离是变化的，以调节提升扭矩和归因于修剪突片（20）的阻力。 该拖曳用于平衡由导弹（4）的运动引起的发射管（2）上的前进摩擦力。 桨距扭矩和线性力同时平衡。

公开(公告)号：US20120068141A1

公开(公告)日：2012-03-22

申请号：US13303276

申请日：2011-11-23

申请人： Kristy A. Campbell ,  John T. Moore

发明人： Kristy A. Campbell ,  John T. Moore

IPC分类号： H01L45/00 ,  H01L21/62

CPC分类号： G11C13/0011 ,  G11C2213/51 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1625

摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition.

摘要翻译： 本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。 根据本发明的实施例，提供了一种电阻可变存储元件，其在玻璃层之间具有至少一个硒化银层，其中至少一个玻璃层是硫族化物玻璃，优选具有GexSe100-x组成。

公开(公告)号：US07863597B2

公开(公告)日：2011-01-04

申请号：US12010420

申请日：2008-01-24

申请人： Kristy A. Campbell ,  Terry L. Gilton ,  John T. Moore ,  Jiutao Li

发明人： Kristy A. Campbell ,  Terry L. Gilton ,  John T. Moore ,  Jiutao Li

IPC分类号： H01L47/00

CPC分类号： H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641 ,  H01L45/1658 ,  H01L45/1683

摘要： A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.

摘要翻译： 形成非易失性电阻可变器件的方法包括在衬底上形成第一导电电极材料。 在第一导电电极材料上形成包含材料的掺杂金属的硫族化物。 这样包括金属和AxBy，其中“B”选自S，Se和Te及其混合物，其中“A”包含至少一种选自第13族，第14族，第15族或第17族的元素 周期表。 在一个方面，将包含硫属元素的材料暴露于HNO 3溶液中。 在一个方面，外表面被有效地氧化以形成包含“A”的氧化物或“B”的氧化物中的至少一种的层。 在一个方面，在包含金属的硫族化物的材料上形成钝化材料。 沉积第二导电电极材料，并且最终由器件的第二导电电极材料形成。