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80 条记录 (耗时 0.041 秒)

    Phase-locked loop and bias generator
    51.
    发明授权
    Phase-locked loop and bias generator 有权
    锁相环和偏置发生器

    公开(公告)号：US08159275B2

    公开(公告)日：2012-04-17

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    Method, Device, and System for Data Communication with Preamble for Reduced Switching Noise
    53.
    发明申请
    Method, Device, and System for Data Communication with Preamble for Reduced Switching Noise 有权
    用于数据通信的方法，设备和系统，用于降低开关噪声

    公开(公告)号：US20110170620A1

    公开(公告)日：2011-07-14

    申请号：US13069259

    申请日：2011-03-22

    申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    IPC分类号： H04L27/00

    CPC分类号： H03M5/145

    摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

    摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

    Semiconductor memory device having low jitter source synchronous interface and clocking method thereof
    54.
    发明授权
    Semiconductor memory device having low jitter source synchronous interface and clocking method thereof 有权
    具有低抖动源同步接口的半导体存储器件及其时钟方法

    公开(公告)号：US07710818B2

    公开(公告)日：2010-05-04

    申请号：US11950279

    申请日：2007-12-04

    申请人： Seung-Jun Bae

    发明人： Seung-Jun Bae

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0812

    摘要： Provided are a semiconductor memory device having a source synchronous interface capable of reducing jitter while minimizing overhead and a clocking method thereof. The semiconductor memory device comprises a phase locked loop (PLL) circuit receiving a first external clock signal for a command and address signal and generating a first internal clock signal, a first delay locked loop (DLL) circuit receiving a second external clock signal for predetermined bits of data and the first internal clock signal and generating a second internal clock signal locked to the second external clock signal, and a second DLL circuit receiving a third external clock signal for the remaining bits of the data and the first internal clock signal and generating a third internal clock signal locked to the third external clock signal.

    摘要翻译： 提供了具有能够减少抖动同时最小化开销的源同步接口及其时钟方法的半导体存储器件。 半导体存储器件包括锁相环（PLL）电路，接收用于命令和地址信号的第一外部时钟信号并产生第一内部时钟信号;第一延迟锁定环（DLL）电路，接收第二外部时钟信号以预定 数据位和第一内部时钟信号，并产生锁定到第二外部时钟信号的第二内部时钟信号，以及第二DLL电路，接收数据的剩余位和第一内部时钟信号的第三外部时钟信号，并产生 第三个内部时钟信号锁定到第三个外部时钟信号。

    Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments
    56.
    发明申请
    Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments 有权
    具有相位和增益调整的具有噪声消除电路的半导体存储器接口装置的方法

    公开(公告)号：US20130215694A1

    公开(公告)日：2013-08-22

    申请号：US13790306

    申请日：2013-03-08

    申请人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-II Park

    发明人： Tae-Young Oh ,  Seung-Jun Bae ,  Kwnag-II Park

    IPC分类号： G11C7/10

    CPC分类号： G11C7/10 ,  G11C7/02

    摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

    摘要翻译： 提供了一种存储器接口电路，包括：第一信号输出电路，被配置为经由第一信号线将第一信号输出到第一I / O端子; 第二信号输出电路，被配置为经由第二信号线将第二信号输出到第二I / O端子; 以及噪声消除电路，其具有至少一个相位调整元件和至少一个增益调整元件，以减少由于在第一信号线上存在第一信号而在第二信号线上感应到的噪声信号，其中第二信号线是 设置在第一信号线附近。

    Voltage-controlled oscillator and phase-locked loop circuit
    57.
    发明授权
    Voltage-controlled oscillator and phase-locked loop circuit 有权
    压控振荡器和锁相环电路

    公开(公告)号：US08400818B2

    公开(公告)日：2013-03-19

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C7/00

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    Method, device, and system for data communication with preamble for reduced switching noise
    58.
    发明授权
    Method, device, and system for data communication with preamble for reduced switching noise 有权
    用于与前同步码进行数据通信以减少开关噪声的方法，设备和系统

    公开(公告)号：US07936289B2

    公开(公告)日：2011-05-03

    申请号：US12655624

    申请日：2010-01-04

    申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    IPC分类号： H03M5/00

    CPC分类号： H03M5/145

    摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

    摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

    Receiving apparatus and method thereof
    59.
    发明授权
    Receiving apparatus and method thereof 有权
    接收装置及其方法

    公开(公告)号：US07822111B2

    公开(公告)日：2010-10-26

    申请号：US11345451

    申请日：2006-02-02

    申请人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

    发明人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03038 ,  H04L7/0058

    摘要： Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.

    摘要翻译： 示例性实施例涉及一种接收设备及其方法。 在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。 均衡接收单元可以在初始设置模式中确定偏移值和均衡系数，并且可以基于所确定的偏移值和均衡系数来调整接收的数据信号。

    Majority voter circuits and semiconductor device including the same
    60.
    发明申请
    Majority voter circuits and semiconductor device including the same 审中-公开
    多数选民电路和半导体器件包括相同

    公开(公告)号：US20100148819A1

    公开(公告)日：2010-06-17

    申请号：US12656590

    申请日：2010-02-04

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-II Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-II Park

    IPC分类号： H03K19/23 ,  H03K19/20

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。