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    MEMORY SYSTEM AND METHOD
    2.
    发明申请
    MEMORY SYSTEM AND METHOD 审中-公开
    记忆系统和方法

    公开(公告)号：US20140019833A1

    公开(公告)日：2014-01-16

    申请号：US14031620

    申请日：2013-09-19

    申请人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    发明人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  H03M13/09

    摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

    摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

    Data receiver having an integration unit and a sense amplification unit, and semiconductor memory device including the same
    3.
    发明授权
    Data receiver having an integration unit and a sense amplification unit, and semiconductor memory device including the same 有权
    具有集成单元和感测放大单元的数据接收器以及包括该单元的半导体存储器件

    公开(公告)号：US08467255B2

    公开(公告)日：2013-06-18

    申请号：US13162948

    申请日：2011-06-17

    申请人： Dae-Hyun Kim ,  Seung-Jun Bae

    发明人： Dae-Hyun Kim ,  Seung-Jun Bae

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1084 ,  G11C7/1087

    摘要： A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal

    摘要翻译： 存储器件中的数据接收器包括积分单元，感测放大单元和锁存单元。 积分单元积分数据信号，以响应于采样反馈信号产生第一均衡信号。 数据信号包括顺序接收的多个数据。 感测放大单元响应于感测反馈信号感测第一均衡信号以产生第二均衡信号。 锁存单元锁存第二均衡信号以产生采样数据信号

    Semiconductor memory device having power-saving effect
    4.
    发明授权
    Semiconductor memory device having power-saving effect 有权
    具有省电效果的半导体存储器件

    公开(公告)号：US08254201B2

    公开(公告)日：2012-08-28

    申请号：US12797791

    申请日：2010-06-10

    申请人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    发明人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    IPC分类号： G11C8/18 ,  G11C7/10

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/2227 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

    摘要翻译： 半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。 存储单元阵列包括多个存储单元，并被配置为存储数据。 当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号 设备。 数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

    Method, device, and system for data communication with preamble for reduced switching noise
    5.
    发明授权
    Method, device, and system for data communication with preamble for reduced switching noise 有权
    用于与前同步码进行数据通信以减少开关噪声的方法，设备和系统

    公开(公告)号：US08199035B2

    公开(公告)日：2012-06-12

    申请号：US13069259

    申请日：2011-03-22

    申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    IPC分类号： H03M7/00

    CPC分类号： H03M5/145

    摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

    摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

    Phase-locked loop and bias generator
    6.
    发明授权
    Phase-locked loop and bias generator 有权
    锁相环和偏置发生器

    公开(公告)号：US08159275B2

    公开(公告)日：2012-04-17

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    Method, Device, and System for Data Communication with Preamble for Reduced Switching Noise
    8.
    发明申请
    Method, Device, and System for Data Communication with Preamble for Reduced Switching Noise 有权
    用于数据通信的方法，设备和系统，用于降低开关噪声

    公开(公告)号：US20110170620A1

    公开(公告)日：2011-07-14

    申请号：US13069259

    申请日：2011-03-22

    申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

    IPC分类号： H04L27/00

    CPC分类号： H03M5/145

    摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

    摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

    Semiconductor memory device having low jitter source synchronous interface and clocking method thereof
    9.
    发明授权
    Semiconductor memory device having low jitter source synchronous interface and clocking method thereof 有权
    具有低抖动源同步接口的半导体存储器件及其时钟方法

    公开(公告)号：US07710818B2

    公开(公告)日：2010-05-04

    申请号：US11950279

    申请日：2007-12-04

    申请人： Seung-Jun Bae

    发明人： Seung-Jun Bae

    IPC分类号： G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0812

    摘要： Provided are a semiconductor memory device having a source synchronous interface capable of reducing jitter while minimizing overhead and a clocking method thereof. The semiconductor memory device comprises a phase locked loop (PLL) circuit receiving a first external clock signal for a command and address signal and generating a first internal clock signal, a first delay locked loop (DLL) circuit receiving a second external clock signal for predetermined bits of data and the first internal clock signal and generating a second internal clock signal locked to the second external clock signal, and a second DLL circuit receiving a third external clock signal for the remaining bits of the data and the first internal clock signal and generating a third internal clock signal locked to the third external clock signal.

    摘要翻译： 提供了具有能够减少抖动同时最小化开销的源同步接口及其时钟方法的半导体存储器件。 半导体存储器件包括锁相环（PLL）电路，接收用于命令和地址信号的第一外部时钟信号并产生第一内部时钟信号;第一延迟锁定环（DLL）电路，接收第二外部时钟信号以预定 数据位和第一内部时钟信号，并产生锁定到第二外部时钟信号的第二内部时钟信号，以及第二DLL电路，接收数据的剩余位和第一内部时钟信号的第三外部时钟信号，并产生 第三个内部时钟信号锁定到第三个外部时钟信号。