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    Semiconductor devices, methods of operating semiconductor devices, and systems having the same
    1.
    发明授权
    Semiconductor devices, methods of operating semiconductor devices, and systems having the same 有权
    半导体器件，半导体器件的操作方法以及具有该半导体器件的系统

    公开(公告)号：US08306169B2

    公开(公告)日：2012-11-06

    申请号：US12318773

    申请日：2009-01-08

    申请人： Jin Gook Kim ,  Dae Hyun Chung ,  Seung Jun Bae ,  Seung Hoon Lee ,  Won Hwa Shin

    发明人： Jin Gook Kim ,  Dae Hyun Chung ,  Seung Jun Bae ,  Seung Hoon Lee ,  Won Hwa Shin

    IPC分类号： H04L12/66

    CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107 ,  H04L7/0008 ,  H04L7/0091

    摘要： A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing the data output from the memory core and outputting serialized data to the controller via the data port. The first selection signal is generated by the controller based on at least one of the voltage signal and the data output to the controller via the data port.

    摘要翻译： 半导体器件包括选择电路和相位检测器。 选择电路响应于从控制器输出的第一选择信号，作为定时信号输出从控制器输出的第一时钟信号或使用第一时钟信号作为第一输入的PLL的输出信号。 相位检测器产生指示从控制器输出的第二时钟信号与从选择电路输出的定时信号之间的相位差的电压信号。 半导体器件还包括响应于从选择电路输出的定时信号的数据端口，存储数据的存储器核心和串行器，串行化从存储器核心输出的数据，并经由数据端口将串行数据输出到控制器 。 第一选择信号由控制器基于电压信号和通过数据端口输出到控制器的数据中的至少一个来产生。

    Level shifter of semiconductor device and method for controlling duty ratio in the device
    3.
    发明授权
    Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
    半导体器件的电平移位器和装置中占空比的控制方法

    公开(公告)号：US07737748B2

    公开(公告)日：2010-06-15

    申请号：US11986841

    申请日：2007-11-27

    申请人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

    发明人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

    IPC分类号： H03K3/017

    CPC分类号： H03K3/35613 ,  H03K3/017

    摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.

    摘要翻译： 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

    Memory system including a power divider on a multi module memory bus
    4.
    发明授权
    Memory system including a power divider on a multi module memory bus 有权
    存储系统包括多模块存储器总线上的功率分配器

    公开(公告)号：US07646212B2

    公开(公告)日：2010-01-12

    申请号：US11668397

    申请日：2007-01-29

    申请人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    发明人： Myung-Hee Sung ,  Jin-Gook Kim ,  Joung-Ho Kim ,  Jong-Hoon Kim

    IPC分类号： H03K19/003

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C5/14

    摘要： A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

    摘要翻译： 存储器系统包括存储器控制器，传输总线，功率分配器，第一存储器芯片和第二存储器芯片。 传输总线从存储器控制器耦合到功率分配器的第一节点，用于传送信号。 功率分配器的第一节点通过第一线耦合到功率分配器的第二节点，并且第一节点也经由第二线路耦合到功率分配器的第三节点。 第一存储器芯片经由第一分支总线耦合到第二节点，并且第二存储器芯片经由第二分支总线耦合到第三节点。 因此，可以减少由于阻抗不匹配引起的反射波，以增强信号完整性。

    TEMPERATURE SENSING CIRCUIT AND METHOD USING DLL
    5.
    发明申请
    TEMPERATURE SENSING CIRCUIT AND METHOD USING DLL 有权
    温度感测电路和使用DLL的方法

    公开(公告)号：US20080297228A1

    公开(公告)日：2008-12-04

    申请号：US12130117

    申请日：2008-05-30

    申请人： Jin-Gook KIM

    发明人： Jin-Gook KIM

    IPC分类号： H03K3/42

    CPC分类号： H03K5/133 ,  G01K7/01 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  H03K2005/00039 ,  H03L7/0814

    摘要： A temperature sensing circuit using a delay locked loop and a temperature sensing method. The temperature sensing circuit includes a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature. A variable delay unit may have a chain structure of a plurality of delay cells depending upon temperature. The variable delay unit may receive the external clock and generate variable delay pulses having respectively different delay amounts based on temperature. A decision control unit is configured to sense a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. Accordingly, an unnecessary time and cost causable by temperature compensation can be reduced, and an automatic temperature compensation and a precise temperature sensing operation can be obtained.

    摘要翻译： 使用延迟锁定环路的温度检测电路和温度检测方法。 温度检测电路包括锁定延迟单元，用于接收外部时钟并产生锁定的延迟脉冲，保持恒定的延迟量而不管温度如何。 可变延迟单元可以具有取决于温度的多个延迟单元的链结构。 可变延迟单元可以接收外部时钟并产生基于温度分别具有不同延迟量的可变延迟脉冲。 判定控制单元被配置为通过使用从可变延迟脉冲和锁定延迟脉冲之间选择的一个之间的相位差来感测确定温度。 因此，可以降低由温度补偿导致的不必要的时间和成本，并且可以获得自动温度补偿和精确的温度感测操作。

    Level shifter of semiconductor device and method for controlling duty ratio in the device
    6.
    发明申请
    Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
    半导体器件的电平移位器和装置中占空比的控制方法

    公开(公告)号：US20080186075A1

    公开(公告)日：2008-08-07

    申请号：US11986841

    申请日：2007-11-27

    申请人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

    发明人： Jin-Gook Kim ,  Seung-Jun Bae ,  Dae-Hyun Chung

    IPC分类号： H03L5/00

    CPC分类号： H03K3/35613 ,  H03K3/017

    摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.

    摘要翻译： 提供半导体器件的电平移位器和控制占空比的方法。 电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管 施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出 控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    7.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US08151010B2

    公开(公告)日：2012-04-03

    申请号：US12902328

    申请日：2010-10-12

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Temperature sensing circuit and method using DLL
    9.
    发明授权
    Temperature sensing circuit and method using DLL 有权
    温度感应电路及其使用方法

    公开(公告)号：US07772915B2

    公开(公告)日：2010-08-10

    申请号：US12130117

    申请日：2008-05-30

    申请人： Jin-Gook Kim

    发明人： Jin-Gook Kim

    IPC分类号： H01L35/00 ,  G01K7/00

    CPC分类号： H03K5/133 ,  G01K7/01 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  H03K2005/00039 ,  H03L7/0814

    摘要： A temperature sensing circuit using a delay locked loop and a temperature sensing method. The temperature sensing circuit includes a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature. A variable delay unit may have a chain structure of a plurality of delay cells depending upon temperature. The variable delay unit may receive the external clock and generate variable delay pulses having respectively different delay amounts based on temperature. A decision control unit is configured to sense a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. Accordingly, an unnecessary time and cost causable by temperature compensation can be reduced, and an automatic temperature compensation and a precise temperature sensing operation can be obtained.

    摘要翻译： 使用延迟锁定环路的温度检测电路和温度检测方法。 温度检测电路包括锁定延迟单元，用于接收外部时钟并产生锁定的延迟脉冲，保持恒定的延迟量而不管温度如何。 可变延迟单元可以具有取决于温度的多个延迟单元的链结构。 可变延迟单元可以接收外部时钟并产生基于温度分别具有不同延迟量的可变延迟脉冲。 判定控制单元被配置为通过使用从可变延迟脉冲和锁定延迟脉冲之间选择的一个之间的相位差来感测确定温度。 因此，可以降低由温度补偿导致的不必要的时间和成本，并且可以获得自动温度补偿和精确的温度感测操作。