公开(公告)号：US20060186824A1

公开(公告)日：2006-08-24

申请号：US11352792

申请日：2006-02-13

申请人： Wein-Town Sun

发明人： Wein-Town Sun

IPC分类号： G09G3/10

CPC分类号： G09G3/3241 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0852 ,  G09G2320/0223

摘要： A pixel array comprising a plurality of pixel driving circuits for an electroluminescent device. Each pixel driving circuit comprises a switch transistor, a scan line, a data line, a driving transistor, an electroluminescent device, a storage capacitor and a compensation capacitor. The scan and data lines are respectively connected to first and second terminals of the switch transistor. First and second terminals of the driving transistor are respectively connected to a third terminal of the switch transistor and a first potential. The electroluminescent device is connected between a third terminal of the driving transistor and a second potential. The storage capacitor is connected between the first terminal of the driving transistor and the first potential, or a previous scan line. The compensation capacitor is connected between the first terminals of the switching and driving transistors. Not all compensation capacitors connected to the same scan line have the same capacitance.

摘要翻译： 一种像素阵列，包括用于电致发光器件的多个像素驱动电路。 每个像素驱动电路包括开关晶体管，扫描线，数据线，驱动晶体管，电致发光器件，存储电容器和补偿电容器。 扫描和数据线分别连接到开关晶体管的第一和第二端子。 驱动晶体管的第一和第二端子分别连接到开关晶体管的第三端子和第一电位。 电致发光器件连接在驱动晶体管的第三端和第二电位之间。 存储电容器连接在驱动晶体管的第一端和第一电位之间或先前的扫描线之间。 补偿电容器连接在开关晶体管和驱动晶体管的第一端子之间。 不是所有连接到同一条扫描线的补偿电容都具有相同的电容。

公开(公告)号：US07084843B2

公开(公告)日：2006-08-01

申请号：US10604629

申请日：2003-08-06

申请人： Jian-Shen Yu ,  Wein-Town Sun

发明人： Jian-Shen Yu ,  Wein-Town Sun

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2300/0408

摘要： An integrated driver device frame of a liquid crystal display panel is provided. The integrated driver device frame comprises a plurality of driver units, a plurality of driver lines and a plurality of output terminals. Each output terminal is coupled to a corresponding pixel element respectively. In the integrated driver device frame of the invention, the plurality of driver units is arranged with two staggered rows, in order that the driver unit width is larger than the interval of every neighboring two output terminals and is less than two times of the interval. Accordingly, the interval of two neighboring output terminals can be equal to the pixel pitch and the dot-per-inch resolution of the LCD panel can be enhanced.

摘要翻译： 提供了一种液晶显示面板的集成驱动器装置框架。 集成驱动器装置框架包括多个驱动器单元，多个驱动器线和多个输出端子。 每个输出端分别耦合到相应的像素元件。 在本发明的集成驱动器装置框架中，多个驱动器单元布置有两个交错列，以便驱动器单元宽度大于每个相邻两个输出端子的间隔，并且小于间隔的两倍。 因此，两个相邻输出端子的间隔可以等于像素间距，并且可以提高LCD面板的每英寸点数分辨率。

公开(公告)号：US20060121310A1

公开(公告)日：2006-06-08

申请号：US11005648

申请日：2004-12-07

申请人： Wein-Town Sun

发明人： Wein-Town Sun

IPC分类号： B32B19/00

CPC分类号： H01L27/3265 ,  H01L27/12 ,  H01L27/13

摘要： An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.

摘要翻译： 电致发光（EL）器件包括衬底和形成在衬底上的多个像素。 每个像素包括至少包括第一电容器和第二电容器的第一区域，第一电容器包括第一导电层，第一导电层上的第一电介质层和第一介电层上的第二导电层， 包括第二导电层的电容器，在第二导电层上的第二电介质层，以及在第二介电层上的第三导电层，以及包括形成在衬底上的第一半导体层的第二区域， 半导体层和第一栅极氧化物层上的第四导电层。

公开(公告)号：US20050270206A1

公开(公告)日：2005-12-08

申请号：US11125992

申请日：2005-05-10

申请人： Jung-Chun Tseng ,  Shin-Hung Yeh ,  Wein-Town Sun

发明人： Jung-Chun Tseng ,  Shin-Hung Yeh ,  Wein-Town Sun

IPC分类号： G09G3/20 ,  G09G3/32 ,  H03M1/66

CPC分类号： G09G3/3275 ,  G09G3/2025 ,  G09G3/2081 ,  G09G2310/027

摘要： A data driving circuit and organic light emitting diode display, comprising a D/A converter, a switch unit, a first analog sampling storage circuit and a second analog sampling storage circuit. The first analog sampling storage circuit is controlled by a first signal for storing corresponding first analog transformed data in the first cycle, and controlled by a second signal for outputting first analog data corresponding to the first analog transformed data in the second cycle. The second analog sampling storage circuit is controlled by the second signal for storing the second analog transformed data in the second cycle, and controlled by the first signal for outputting second analog data corresponding to the second analog transformed data in a third cycle.

摘要翻译： 数据驱动电路和有机发光二极管显示器，包括D / A转换器，开关单元，第一模拟采样存储电路和第二模拟采样存储电路。 第一模拟采样存储电路由用于在第一周期中存储对应的第一模拟变换数据的第一信号控制，并由第二信号控制，用于在第二周期中输出对应于第一模拟变换数据的第一模拟数据。 第二模拟采样存储电路由第二信号控制，用于在第二周期中存储第二模拟变换数据，并由第一信号控制，用于在第三周期中输出对应于第二模拟变换数据的第二模拟数据。

公开(公告)号：US20050179624A1

公开(公告)日：2005-08-18

申请号：US10776177

申请日：2004-02-12

申请人： Wein-Town Sun

发明人： Wein-Town Sun

IPC分类号： G09F9/30 ,  G09G3/30 ,  G09G3/32 ,  H01J1/62 ,  H05B33/00

CPC分类号： G09G3/3241 ,  G09G2300/0842

摘要： A pixel device of an electroluminescence device that comprises a voltage signal having a first state and a second state, a current signal, a first circuit further comprising a first transistor, a second transistor and a capacitor, the capacitor including a first terminal coupled to a power supply, the first transistor including a gate electrode coupled to a second terminal of the capacitor, and the second transistor including a gate electrode receiving the voltage signal, wherein the first circuit provides a voltage level across the capacitor in response to the first state of the voltage signal, and maintains the voltage level in response to the second state of the voltage signal, and a second circuit further comprising a third transistor and a fourth transistor, the third transistor including a gate electrode coupled to a gate electrode of the fourth transistor, wherein the second circuit provides a current proportional to the magnitude of the current signal in response to the first state of the voltage signal, and the first circuit provides a sum current of the proportional current and the current signal.

摘要翻译： 一种电致发光器件的像素器件，包括具有第一状态和第二状态的电压信号，电流信号，还包括第一晶体管，第二晶体管和电容器的第一电路，所述电容器包括耦合到 所述第一晶体管包括耦合到所述电容器的第二端子的栅电极，并且所述第二晶体管包括接收所述电压信号的栅电极，其中所述第一电路响应于所述电容器的第一状态而在所述电容器两端提供电压电平 电压信号，并且响应于电压信号的第二状态而保持电压电平，第二电路还包括第三晶体管和第四晶体管，第三晶体管包括耦合到第四晶体管的栅电极的栅电极 ，其中所述第二电路响应于所述第一电路提供与所述电流信号的幅度成比例的电流 电压信号的电位，第一电路提供比例电流和电流信号的和电流。

公开(公告)号：US20050122290A1

公开(公告)日：2005-06-09

申请号：US10820837

申请日：2004-04-07

申请人： Wein-Town Sun

发明人： Wein-Town Sun

IPC分类号： G09G3/32 ,  G09G3/36

CPC分类号： G09G3/325 ,  G09G3/3233 ,  G09G3/3241 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2320/0252 ,  G09G2330/025

摘要： The present invention provides a circuit for driving a flat panel display, including a storage capacitor, a transmission gate and a current-limiting transistor. A first terminal of the storage capacitor is coupled to a system voltage, and a second terminal of the storage capacitor is at storage voltage. A first input/output terminal of the transmission gate is coupled to the storage voltage, and the second input/output terminal of the transmission gate is coupled to the data current source. A first gate terminal of the transmission gate is coupled to the first signal; a second gate terminal of the transmission gate is coupled to the second signal. A gate terminal of the current-limiting transistor is coupled to the storage voltage, wherein a first source/drain terminal is coupled to the system voltage, and a second source/drain terminal provides current for driving the flat panel display.

摘要翻译： 本发明提供一种用于驱动平板显示器的电路，包括存储电容器，传输门极和限流晶体管。 存储电容器的第一端子耦合到系统电压，并且存储电容器的第二端子处于存储电压。 传输门的第一输入/输出端耦合到存储电压，并且传输门的第二输入/输出端耦合到数据电流源。 传输门的第一门极耦合到第一信号; 传输门的第二门极耦合到第二信号。 限流晶体管的栅极端子耦合到存储电压，其中第一源极/漏极端子耦合到系统电压，并且第二源极/漏极端子提供用于驱动平板显示器的电流。

公开(公告)号：US06839398B2

公开(公告)日：2005-01-04

申请号：US10379131

申请日：2003-03-04

申请人： Wein-Town Sun

发明人： Wein-Town Sun

IPC分类号： G11C19/00 ,  G11C19/28

CPC分类号： G11C19/00 ,  G11C19/28

摘要： A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level. The level shifting circuit includes a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD, a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD, a first inverse logic gate coupled to the first drain and having an output terminal, a second inverse logic gate coupled to the second drain and having an inverse output terminal coupled to the input circuit, a first NMOS transistor having a third gate coupled to the input circuit, a third drain coupled to the first drain and a third source coupled to a second voltage VSS, a second NMOS transistor having a fourth gate coupled to the second gate and a fourth drain coupled to the second drain and a fourth source coupled to the second voltage VSS. The output circuit is coupled to the output terminal for outputting the shift-register signal.

摘要翻译： 移位寄存器电路。 当输入脉冲处于高电压电平时，输入电路接收输入脉冲并输出高电平电平输入信号。 电平移位电路包括具有第一栅极，第一漏极和耦合到第一电压VDD的第一源极的第一PMOS晶体管，具有耦合到第一漏极的第二栅极的第二PMOS晶体管，耦合到第一栅极的第二漏极 以及耦合到所述第一电压VDD的第二源极，耦合到所述第一漏极并具有输出端的第一反逻辑门，耦合到所述第二漏极并具有耦合到所述输入电路的反相输出端的第二反逻辑门， 第一NMOS晶体管，具有耦合到输入电路的第三栅极，耦合到第一漏极的第三漏极和耦合到第二电压VSS的第三源极，具有耦合到第二栅极的第四栅极的第二NMOS晶体管和耦合到第二漏极的第四漏极 到第二漏极和耦合到第二电压VSS的第四源极。 输出电路耦合到输出端，用于输出移位寄存器信号。

公开(公告)号：US06819277B1

公开(公告)日：2004-11-16

申请号：US10604896

申请日：2003-08-25

申请人： Jen-Yi Hu ,  Wein-Town Sun

发明人： Jen-Yi Hu ,  Wein-Town Sun

IPC分类号： H03M166

CPC分类号： H03M1/682 ,  H03M1/765

摘要： A method is used for reducing spikes in a digital-to-analog converter (DAC), which includes a plurality of digit circuits for transforming a digital voltage signal into an analog voltage signal. The method includes receiving the digital voltage signal, setting the digit circuit corresponding to a predetermined bit of the digital voltage signal closest to an output module, and outputting an analog voltage signal corresponding to the digital voltage signal, wherein the predetermined bit of the digital voltage signal is the bit with least signal variation among the bits of the digital voltage signal.

摘要翻译： 一种用于减少数模转换器（DAC）中的尖峰的方法，数模转换器（DAC）包括用于将数字电压信号变换为模拟电压信号的多个数字电路。 该方法包括接收数字电压信号，设置与最接近输出模块的数字电压信号的预定位相对应的数字电路，并输出对应于数字电压信号的模拟电压信号，其中数字电压的预定位 信号是在数字电压信号的位之间具有最小信号变化的位。

公开(公告)号：US20140073126A1

公开(公告)日：2014-03-13

申请号：US13610875

申请日：2012-09-12

申请人： Cheng-Yen Shen ,  Wein-Town Sun

发明人： Cheng-Yen Shen ,  Wein-Town Sun

IPC分类号： H01L21/28

CPC分类号： H01L27/11573 ,  H01L21/28273 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/11529 ,  H01L27/11546

摘要： A method of manufacturing a non-volatile memory is provided. A substrate includes a memory cell region and a first periphery circuit region. The memory cell region includes a select transistor region. A first gate dielectric layer having a first thickness is formed on the substrate in the first periphery circuit region and the select transistor region. A portion of the first gate dielectric layer on the select transistor region is removed to form a second gate dielectric layer. The second dielectric layer has a second thickness, wherein the second thickness is less than the first thickness.

摘要翻译： 提供一种制造非易失性存储器的方法。 衬底包括存储单元区域和第一外围电路区域。 存储单元区域包括选择晶体管区域。 在第一外围电路区域和选择晶体管区域的基板上形成具有第一厚度的第一栅极介质层。 去除选择晶体管区域上的第一栅极电介质层的一部分以形成第二栅极介电层。 第二介电层具有第二厚度，其中第二厚度小于第一厚度。

公开(公告)号：US08288774B2

公开(公告)日：2012-10-16

申请号：US13348715

申请日：2012-01-12

申请人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

发明人： Wein-Town Sun ,  Chun-Sheng Li ,  Jian-Shen Yu

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/04 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108

CPC分类号： H01L29/78645 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/78621

摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.

摘要翻译： 公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。 该布局包括（1）在基底上的多晶硅，其具有顶部具有L-或蛇形的形状，具有重掺杂的源极区，第一轻掺杂区，第一栅极通道，第二轻掺杂区， 第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层上形成栅极金属层，并且具有L形或I形的延伸部分 。 栅极金属与多晶硅层相交，限定了前述栅极沟道。 在栅极通道中，至少有一个沿着信号线通过源极接触。