公开(公告)号：US06955955B2

公开(公告)日：2005-10-18

申请号：US10747494

申请日：2003-12-29

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Hung-Wei Chen ,  Di-Hong Lee ,  Chuan-Ping Hou ,  Jhi-Cherng Lu

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01

CPC分类号： H01L21/76224 ,  H01L21/84

摘要： In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.

摘要翻译： 在制造半导体器件的方法中，提供了初始结构。 初始结构包括衬底，图案化硅层和覆盖层。 基板上形成有埋置的绝缘体层。 图案化的硅层形成在掩埋绝缘体层上。 覆盖层形成在图案化硅层上。 在初始结构上形成第一层。 通过蚀刻工艺去除第一层的一部分，使得图案化硅层的侧壁部分被暴露，并且使得第一层的剩余部分保留在图案化硅层与掩埋绝缘体层接合的拐角处。 在暴露的侧壁部分上形成氧化物衬垫。 可以在掩埋绝缘体层（在形成第一层之前）形成凹部，并且可以在图案化的硅层的部分下方延伸。

公开(公告)号：US20050215017A1

公开(公告)日：2005-09-29

申请号：US10807081

申请日：2004-03-23

申请人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

发明人： Hung-Wei Chen ,  Hsun-Chin Tsao ,  Kuang-Hsin Chen ,  Di-Houng Lee

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride—silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region. A second embodiment features the formation of a dielectric barrier layer on the surfaces of STI openings preventing boron from segregated to silicon oxide filled STI regions. A combination of both embodiments can be employed to reduce and prevent boron segregation to both underlying and adjacent insulator regions, thus reducing the risk of short channel phenomena.

摘要翻译： 已经开发了减少在SOI层中形成的NMOS器件的短通道现象的方法，其中通过硼从沟道区域移动到相邻的绝缘体区域产生短沟道现象。 本发明的第一实施例需要形成位于NMOS器件下面的硼或氮掺杂的绝缘体层。 这是通过在复合氮化硅 - 硅形状中形成浅沟槽开口而实现的，随后氮化硅形状的横向拉回暴露出硅形状的顶表面的部分，然后将硼或氮离子注入到 绝缘体层暴露在STI开口中并且沉积在硅形状的暴露部分下面的绝缘体层的部分中。 随后的氢退火程序完成掺杂的绝缘体层，其减轻了从上覆的NMOS沟道区域的硼偏析。 第二实施例的特征在于在STI开口的表面上形成介电阻挡层，防止硼偏析到填充氧化硅的STI区域。 可以采用两种实施方案的组合来减少和防止硼分离到下面的和相邻的绝缘体区域，从而降低短沟道现象的风险。

公开(公告)号：US06691376B1

公开(公告)日：2004-02-17

申请号：US10223742

申请日：2002-08-20

申请人： Hung-Wei Chen

发明人： Hung-Wei Chen

IPC分类号： A44B2100

CPC分类号： B42F1/10 ,  B42P2241/10 ,  B42P2241/28 ,  Y10T24/20 ,  Y10T24/201 ,  Y10T24/207 ,  Y10T24/44821 ,  Y10T24/44855 ,  Y10T24/44923

摘要： A firmly secured paper clip comprises a foldable paper clip and a retainer. The paper clip is capable of being folded as three paper plates. The first paper plate is the longest one, and the third paper plate is the shortest one. The first paper plate is connected to the second paper plate and the second paper plate is connected to the third paper plate. In assembly, the second paper plate is folded and then is adhered on the first paper plate. Then the third paper plate is folded from the second paper plate and is located between the first paper plate and second paper plate. The retainer serves to fix the first paper plate and second paper plate to form the whole paper clip. Thereby, when a notepaper is inserted into a clamping opening between the first paper plate and third paper plate, it is firmly secured therein.

摘要翻译： 牢固固定的回形针包括可折叠的回形针和保持器。 纸夹能够折叠成三张纸板。 第一个纸板是最长的纸板，第三个纸板是最短的。 第一纸板连接到第二纸板，第二纸板连接到第三纸板。 在组装时，第二纸板被折叠，然后粘附在第一纸板上。 然后，第三纸板从第二纸板折叠并且位于第一纸板和第二纸板之间。 保持器用于固定第一纸板和第二纸板以形成整个回形针。 因此，当将纸条插入到第一纸板和第三纸板之间的夹紧开口中时，其牢固地固定在其中。

公开(公告)号：US6026676A

公开(公告)日：2000-02-22

申请号：US887144

申请日：1997-07-02

申请人： Hung-Wei Chen ,  Teng-Chien Yu ,  Ming-Hung Su ,  Yi-An Chen ,  Philip Yong

发明人： Hung-Wei Chen ,  Teng-Chien Yu ,  Ming-Hung Su ,  Yi-An Chen ,  Philip Yong

IPC分类号： G01B17/08 ,  G11B5/60 ,  G11B5/82 ,  G11B19/04 ,  G11B33/10

CPC分类号： G11B5/6005 ,  G01B17/08 ,  G11B5/82 ,  G11B19/04 ,  G11B33/10

摘要： A glide head with mounted PZT sensor is used to obtain a glide avalanche curve. The glide head is subsequently gradually decreased until the signal is extremely high. First, at least one resonance frequency of the glide head is determined. The frequency component of the PZT glide signal to each specific irregular peak is analyzed by using the speed of the glide head divided by the bump spacing, multiplied by a factor, m, where m is an integer number. The next step of the present invention is to determine a glide avalanche break point of the recording medium. Then, the glide avalanche point is determined in the region which is between the irregular peaks and the extremely high signal.

摘要翻译： 使用带有PZT传感器的滑翔头来获得滑行雪崩曲线。 随后，滑翔头逐渐减小，直到信号极高。 首先，确定滑行头的至少一个共振频率。 通过使用滑移头的速度除以凸起间距乘以因子m，其中m是整数来分析PZT滑翔信号对每个特定不规则峰值的频率分量。 本发明的下一步是确定记录介质的滑动雪崩断裂点。 然后，在不规则峰值和极高信号之间的区域中确定滑动雪崩点。

公开(公告)号：US09207330B2

公开(公告)日：2015-12-08

申请号：US13343237

申请日：2012-01-04

申请人： Fan-Ren Chang ,  He-Sheng Wang ,  Hung-Wei Chen ,  Chih-Horng Li ,  Shu-Min Chuang ,  Ping-Feng Wang ,  Chih-Min Hsu ,  Shan-Yuan Yang

发明人： Fan-Ren Chang ,  He-Sheng Wang ,  Hung-Wei Chen ,  Chih-Horng Li ,  Shu-Min Chuang ,  Ping-Feng Wang ,  Chih-Min Hsu ,  Shan-Yuan Yang

IPC分类号： G01S19/40

CPC分类号： G01S19/40

摘要： A positioning device and a positioning method thereof are provided. The positioning device can cooperate with a first satellite group and a second satellite group, and it comprises a storage, a receiver and a processor. The receiver is configured to receive a first satellite group signal from the first satellite group and a second satellite group signal from the second satellite group. The processor is electrically connected to the storage and the receiver, and configured to calculate a positioning offset value according to one of the first satellite group signal and the second satellite group signal. In addition, the processor is configured to calculate a positioning result according to the second satellite group signal and the positioning offset, and store the positioning result in the storage.

摘要翻译： 提供了一种定位装置及其定位方法。 定位装置可以与第一卫星组和第二卫星组合作，并且其包括存储器，接收器和处理器。 接收机被配置为从第一卫星组接收第一卫星组信号和从第二卫星组接收第二卫星组信号。 处理器电连接到存储器和接收器，并且被配置为根据第一卫星组信号和第二卫星组信号中的一个来计算定位偏移值。 此外，处理器被配置为根据第二卫星组信号和定位偏移来计算定位结果，并将定位结果存储在存储器中。

公开(公告)号：US08148996B2

公开(公告)日：2012-04-03

申请号：US11798000

申请日：2007-05-09

申请人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

发明人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/31935

摘要： The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.

摘要翻译： 本发明公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括逻辑测试器和信号测量模块。 逻辑测试器耦合到被测器件，以提供测试信号和触发信号，然后根据数字测量结果确定被测器件的测试结果。 耦合到待测器件的信号测量模块和逻辑测试器，用于在接收到触发信号之后根据测试信号测量被测器件产生的直流信号，并产生数字测量结果。

公开(公告)号：US20100227447A1

公开(公告)日：2010-09-09

申请号：US12399124

申请日：2009-03-06

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/11519 ,  H01L29/40114

摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

摘要翻译： 闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

公开(公告)号：US07705670B2

公开(公告)日：2010-04-27

申请号：US12232353

申请日：2008-09-16

申请人： Hung-Wei Chen ,  Po-Yin Chao

发明人： Hung-Wei Chen ,  Po-Yin Chao

IPC分类号： H03F1/02

CPC分类号： H03G3/3031

摘要： A first gain stage and a second gain stage having different gains are linked in cascade to construct a wide range and high resolution programmable gain amplifier. The second gain stage can be used only for low gain and low power consumption. Furthermore, two pairs of chopper circuits are used to shift flicker noise when the programmable gain amplifier is operated.

摘要翻译： 具有不同增益的第一增益级和第二增益级联级联以构建宽范围和高分辨率可编程增益放大器。 第二增益级只能用于低增益和低功耗。 此外，当可编程增益放大器工作时，两对斩波电路用于移位闪烁噪声。

公开(公告)号：US07663185B2

公开(公告)日：2010-02-16

申请号：US11441724

申请日：2006-05-27

申请人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

发明人： Kuang-Hsin Chen ,  Hsun-Chih Tsao ,  Jhi-Cherng Lu ,  Chuan-Ping Hou ,  Peng-Fu Hsu ,  Hung-Wei Chen ,  Di-Hong Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

摘要翻译： 翅片FET器件及其制造方法都采用体半导体衬底。 在体半导体衬底内形成翅片和相邻的槽。 槽部分地用沉积的介电层回填以形成暴露的翅片区域和未曝光的翅片区域。 在暴露的散热片区域上形成栅极电介质层，在栅极电介质层上形成栅电极。 通过采用体半导体衬底，成本有效地制造了鳍式FET器件。

公开(公告)号：US07642801B2

公开(公告)日：2010-01-05

申请号：US11898317

申请日：2007-09-11

申请人： Cheng-Yung Teng ,  Hung-Wei Chen

发明人： Cheng-Yung Teng ,  Hung-Wei Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/31932 ,  G01R31/31924

摘要： A circuit testing apparatus for testing a device under test is disclosed. The circuit testing apparatus includes a function generator, a signal measuring module and a determining module. The function generator is coupled to the device under test for providing a plurality of testing signals according to a predetermined manner. The signal measuring module is coupled to the device under test and the function module for measuring a plurality of measuring signals generated by the device under test according to the plurality of testing signals and generating a plurality of measuring results according to the predetermined manner. The determining module is coupled to the signal measuring module for determining a testing result for the device under test according to the plurality of measuring results.

摘要翻译： 公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括功能发生器，信号测量模块和确定模块。 功能发生器耦合到被测设备，以根据预定的方式提供多个测试信号。 信号测量模块耦合到被测设备和功能模块，用于根据多个测试信号测量被测器件产生的多个测量信号，并根据预定方式产生多个测量结果。 确定模块耦合到信号测量模块，用于根据多个测量结果确定被测设备的测试结果。