公开(公告)号：US5869870A

公开(公告)日：1999-02-09

申请号：US677109

申请日：1996-07-09

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L23/50 ,  H01L23/60 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L23/60 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/13034 ,  H01L2924/13091 ,  H01L2924/14

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

公开(公告)号：US5818086A

公开(公告)日：1998-10-06

申请号：US661659

申请日：1996-06-11

Applicant: Shi-Tron Lin ,  Alex C. Wang ,  Hsin-Chang Lin

Inventor： Shi-Tron Lin ,  Alex C. Wang ,  Hsin-Chang Lin

IPC: H01L27/02 ,  H01L29/74 ,  H01L23/62 ,  H01L29/00 ,  H01L31/111

CPC classification number: H01L27/0248 ,  H01L2924/0002

Abstract: In accordance with the invention, an integrated circuit has a first ESD protection circuit for each input pin which is not adjacent a non-wired IC pin and a second ESD protection circuit for each input pin which is adjacent a non-wired pin. The second ESD protection circuit has a greater ESD protection capability than the first ESD protection circuit. The second ESD protection circuit has a capability of protecting an input pin when an ESD stress occurs at an adjacent non-wired pin. The second ESD protection circuit includes, for example, additional ESD protection elements in comparison to the first ESD protection circuit. Alternatively, the second ESD protection circuit has one ESD protection element which is larger in size or is otherwise different than a corresponding ESD protection element in the first ESD protection circuit. The invention has the advantage of not changing the definition of the non-wired IC pins and also does not cost large amounts of chip real estate because the ESD protection circuit is reinforced for only those input pins which are adjacent non-wired pins. The ESD protection circuit is not reinforced for I/O pins, VDD pins, VSS pins, and input pins which are not adjacent non-wired pins.

Abstract translation: 根据本发明，集成电路具有用于每个输入引脚的不与非有线IC引脚相邻的第一ESD保护电路和用于与非有线引脚相邻的每个输入引脚的第二ESD保护电路。 第二ESD保护电路具有比第一ESD保护电路更大的ESD保护能力。 第二ESD保护电路具有在相邻的非接线引脚处产生ESD应力时保护输入引脚的能力。 与第一ESD保护电路相比，第二ESD保护电路包括例如额外的ESD保护元件。 或者，第二ESD保护电路具有一个ESD保护元件，该ESD保护元件的尺寸较大或者与第一ESD保护电路中相应的ESD保护元件不同。 本发明的优点在于，不改变非有线IC引脚的定义，并且由于ESD保护电路只对那些相邻非有线引脚的输入引脚加强，所以不会花费大量的芯片空间。 对于I / O引脚，VDD引脚，VSS引脚和非相邻引脚的输入引脚，ESD保护电路不加强。

公开(公告)号：US5763919A

公开(公告)日：1998-06-09

申请号：US677034

申请日：1996-07-08

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0266

Abstract: A MOS transistor array structure for an electro-static discharge protection circuit in a semiconductor integrated circuit device, having dispersed parallel discharge paths. The MOS transistor array includes an n-well formed in a silicon substrate of the fabricated semiconductor device. A first dispersed drain region is formed in the n-well, and a source region is formed in the silicon substrate. A second dispersed drain region is formed in both the silicon substrate and the n-well. A gate of the transistor array is formed on the silicon substrate, and a first field oxide region is distributed at least partially in the dispersed drain region, so as to improve the even distribution of electric current in the event of an electro-static discharge. The transistor structure is compatible with a silicided process of device fabrication for fast device operation. Fabrication of the structure does not require additional procedural steps for achieving this compatibility.

Abstract translation: 一种用于半导体集成电路器件中的静电放电保护电路的MOS晶体管阵列结构，具有分散的平行放电路径。 MOS晶体管阵列包括在制造的半导体器件的硅衬底中形成的n阱。 在n阱中形成第一分散的漏极区，并且在硅衬底中形成源极区。 在硅衬底和n阱中形成第二分散漏极区。 晶体管阵列的栅极形成在硅衬底上，并且第一场氧化物区域至少部分地分布在分散的漏极区域中，以便在静电放电的情况下改善电流的均匀分布。 晶体管结构与用于快速器件操作的器件制造的硅化工艺兼容。 结构的制作不需要额外的程序步骤来实现这种兼容性。

公开(公告)号：US5721439A

公开(公告)日：1998-02-24

申请号：US630127

申请日：1996-04-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/0251

Abstract: A MOS transistor structure for an electro-static discharge (ESD) protection circuit of an integrated circuit device. The ESD protection transistor has a structure that comprises a drain diffusion region formed in the silicon substrate of the integrated circuit device, a source diffusion region formed in the silicon substrate, a gate formed in the silicon substrate, and a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands provide substantially uniform diffusion resistance between the drain contacts and the gate while increasing the diffusion resistance of the drain region to a level suitable for ESD current protection. The disclosed MOS transistor structure may be fabricated by a salicide technology-based fabrication procedure that is completely compatible with the salicide technology used for the making of the circuitry for the IC device.

Abstract translation: 一种用于集成电路器件的静电放电（ESD）保护电路的MOS晶体管结构。 ESD保护晶体管具有包括形成在集成电路器件的硅衬底中的漏极扩散区域，形成在硅衬底中的源极扩散区域，形成在硅衬底中的栅极和多个均匀分布的隔离岛的结构 遍及漏极扩散区域。 隔离岛在漏极接触和栅极之间提供基本均匀的扩散电阻，同时将漏极区域的扩散电阻提高到适合于ESD电流保护的水平。 所公开的MOS晶体管结构可以通过基于自对准硅化物技术的制造程序来制造，其完全兼容用于制造用于IC器件的电路的自对准硅化物技术。

公开(公告)号：US4155553A

公开(公告)日：1979-05-22

申请号：US710919

申请日：1976-08-02

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: A63B47/00 ,  A63B63/04 ,  A63B65/12

CPC classification number: A63B65/12 ,  A63B47/00

Abstract: A ball game machine, which after being hit by an incoming ball, will return another ball with a minimum loss of energy. The incoming ball stops at the ball receiver and transmits almost all of its kinetic energy to the machine through proper inertia design. Instantaneously, the recoiling ball receiver mechanically causes a bat to strike a second ball which has been stored in a collector. The incoming ball then drops into the collector and becomes a stored ball so that the operation can be repeated.

Abstract translation: 一个球形游戏机在被一个进球击中后，会以最小的能量损失返回另一个球。 进球在球接收器处停止，并通过适当的惯性设计将几乎所有的动能传递到机器。 瞬间，反弹球接收器机械地使蝙蝠撞击已经存储在收集器中的第二球。 然后，进入的球落入收集器中并变成储存的球，使得可以重复该操作。

公开(公告)号：US07256461B2

公开(公告)日：2007-08-14

申请号：US10696526

申请日：2003-10-29

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.

Abstract translation: 本发明提供了一种组合的FOX和多门结构，用于有效地降低常规现场设备的触发电压，以改善小型驱动I / O电路的NMOS晶体管的鲁棒性，并提高堆叠的ESD性能 -gate电压容限I / O。

公开(公告)号：US07137096B2

公开(公告)日：2006-11-14

申请号：US10797998

申请日：2004-03-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract translation: 芯片具有电源总线，第一金属层和多个内部电子电路。 第一金属层具有多个电力线，其大致平行并且并联电连接到电力总线，用于将电力传递到内部电子电路。 通过根据内部电子电路的自动放置和路由（APR）处理来构成芯片的第二金属层的多个金属线，并且在第二金属层上形成至少一个稀疏区域。 之后，在稀疏区域中配置至少一个供电区域，并与电源总线电连接。

公开(公告)号：US06958896B2

公开(公告)日：2005-10-25

申请号：US10256445

申请日：2002-09-27

Applicant: Shi-Tron Lin ,  Wei-Fan Chen ,  Chen-Hsin Lien

Inventor： Shi-Tron Lin ,  Wei-Fan Chen ,  Chen-Hsin Lien

IPC: H01L27/02 ,  H02H9/04 ,  H02H9/00

CPC classification number: H01L27/0274 ,  H01L2924/0002 ,  H02H9/046 ,  H01L2924/00

Abstract: An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.

Abstract translation: 描述了基于降低触发电压的早期触发MOSFET ESD保护电路。 在正的ESD事件期间产生瞬态负电压并施加到MOSFET的栅极。 本发明改善了ESD性能，并且对于40以下的薄栅极氧化物特别有用。

公开(公告)号：US20050204324A1

公开(公告)日：2005-09-15

申请号：US10797998

申请日：2004-03-10

Applicant: Shi-Tron Lin

Inventor： Shi-Tron Lin

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A chip has a power bus, a first metal layer and a plurality of internal electronic circuits. The first metal layer has a plurality of power lines which are substantially parallel and electrically connected to the power bus in parallel for delivering electrical power to the internal electronic circuits. A plurality of metal lines of a second metal layer of the chip are configured by an automatic place and route (APR) process according to the internal electronic circuits, and at least one sparse area is formed on the second metal layer. Later, at least one supply-power area is configured in the sparse area, and is electrically connected to the power bus.

Abstract translation: 芯片具有电源总线，第一金属层和多个内部电子电路。 第一金属层具有多个电力线，其大致平行并且并联电连接到电力总线，用于将电力传递到内部电子电路。 通过根据内部电子电路的自动放置和路由（APR）处理来构成芯片的第二金属层的多个金属线，并且在第二金属层上形成至少一个稀疏区域。 之后，在稀疏区域中配置至少一个供电区域，并与电源总线电连接。

公开(公告)号：US06850440B2

公开(公告)日：2005-02-01

申请号：US10229925

申请日：2002-08-27

Applicant: Shi-Tron Lin ,  Wei-Fan Chen

Inventor： Shi-Tron Lin ,  Wei-Fan Chen

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/0416

Abstract: A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjacent to the source and drain regions. A first voltage of first polarity is applied to the control gate. A second voltage of first polarity is applied to the drain region, the second voltage being less than about 5.6 volts. A third voltage of second polarity is applied to the source region.

Abstract translation: 一种操作非易失性存储器件的方法包括：向非易失性存储器件提供具有第一导电体的主体，第二导​​电源的源极区域，以及在主体上具有第二导电性的漏极区域，以及位于主体上方的控制栅极 到源极和漏极区域。 第一极性的第一电压施加到控制栅极。 第一极性的第二电压施加到漏极区，第二电压小于约5.6伏。 第二极性的第三电压被施加到源极区域。