公开(公告)号：US20090239342A1

公开(公告)日：2009-09-24

申请号：US12475130

申请日：2009-05-29

申请人： Byung Chul AHN ,  Oh Nam Kwon ,  Heung Lyul Cho

发明人： Byung Chul AHN ,  Oh Nam Kwon ,  Heung Lyul Cho

IPC分类号： H01L21/336

CPC分类号： H01L27/124 ,  G02F1/134363 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/1288

摘要： A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetween to define a pixel area; a second common line crossing the first common line having the gate insulating film therebetween; a thin film transistor connected to the gate line and the data line; a common electrode extending from the second common line in said pixel area; a pixel electrode that is parallel to the common electrode and the second common line; a protective film for covering the thin film transistor; a gate pad having a lower gate pad electrode connected to an upper gate pad electrode through a first contact hole; a common pad having a lower common pad electrode connected to an upper common pad electrode through a second contact hole; and a data pad having a lower data pad electrode connected to an upper data pad electrode provided within a third contact hole.

摘要翻译： 水平电场型薄膜晶体管基板包括：形成在彼此平行的基板上的栅极线和第一公共线; 跨越所述栅极线和所述第一公共线的数据线，其间具有栅极绝缘膜，以限定像素区域; 第二公共线与其间具有栅绝缘膜的第一公共线交叉; 连接到栅极线和数据线的薄膜晶体管; 在所述像素区域中从所述第二公共线延伸的公共电极; 平行于公共电极和第二公共线的像素电极; 用于覆盖薄膜晶体管的保护膜; 栅极焊盘，其具有通过第一接触孔连接到上部栅极焊盘电极的下部栅极焊盘电极; 公共焊盘，其具有通过第二接触孔连接到上公共焊盘电极的下公共焊盘电极; 以及数据焊盘，其具有连接到设置在第三接触孔内的上数据焊盘电极的下数据焊盘电极。

公开(公告)号：US07612838B2

公开(公告)日：2009-11-03

申请号：US10960545

申请日：2004-10-08

申请人： Byoung Ho Lim ,  Soon Sung Yoo ,  Youn Gyoung Chang ,  Heung Lyul Cho

发明人： Byoung Ho Lim ,  Soon Sung Yoo ,  Youn Gyoung Chang ,  Heung Lyul Cho

IPC分类号： G02F1/136

CPC分类号： G02F1/134336 ,  G02F1/133707

摘要： A thin film transistor array substrate for a liquid crystal display panel includes a gate line formed on a substrate. A data line crosses the gate line, thus defining a pixel region. A gate insulating film is positioned between the data line and the gate line. A thin film transistor is formed at a crossing of the gate line and the data line. A passivation film pattern exposes a portion of a drain electrode of the thin film transistor. At least one protrusion is provided to divide the pixel region into a plurality of regions, each of the regions having a different liquid crystal alignment from the other regions. A pixel electrode is connected to the thin film transistor to cover the pixel region excluding the passivation film pattern and the at least one protrusion.

摘要翻译： 用于液晶显示面板的薄膜晶体管阵列基板包括形成在基板上的栅极线。 数据线与栅极线交叉，从而限定像素区域。 栅极绝缘膜位于数据线和栅极线之间。 在栅极线和数据线的交叉处形成薄膜晶体管。 钝化膜图案暴露薄膜晶体管的漏电极的一部分。 提供至少一个突起以将像素区域划分成多个区域，每个区域与其他区域具有不同的液晶取向。 像素电极连接到薄膜晶体管以覆盖除了钝化膜图案和至少一个突起之外的像素区域。

公开(公告)号：US07528918B2

公开(公告)日：2009-05-05

申请号：US11256092

申请日：2005-10-24

申请人： Soon Sung Yoo ,  Youn Gyoung Chang ,  Heung Lyul Cho

发明人： Soon Sung Yoo ,  Youn Gyoung Chang ,  Heung Lyul Cho

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F2001/134372 ,  G02F2001/13629

摘要： A fringe field switching type thin film transistor substrate includes a double layered structure gate line; a data line crossing the gate line, wherein a gate insulating film is formed therebetween; a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode opposing the source electrode; a double layered structure common line parallel to the gate line; a common electrode plate integrated with the transparent conductive layer of the common line and formed in a pixel area defined by the crossing of the gate line and the data line; a pixel electrode slit covering the drain electrode of the thin film transistor and overlapping the common electrode plate, wherein the gate insulating film is formed therebetween in the pixel area; and a data protection pattern covering the data line and the source electrode.

摘要翻译： 条纹场开关型薄膜晶体管基板包括双层结构栅极线; 与栅极线交叉的数据线，其间形成有栅极绝缘膜; 薄膜晶体管，具有连接到栅极线的栅电极，连接到数据线的源电极和与源电极相对的漏电极; 平行于栅极线的双层结构公共线; 与公共线的透明导电层集成并形成在由栅极线与数据线的交叉限定的像素区域中的公共电极板; 覆盖所述薄膜晶体管的漏电极且与所述公共电极板重叠的像素电极狭缝，其中，在所述像素区域中形成所述栅极绝缘膜; 以及覆盖数据线和源电极的数据保护图案。

公开(公告)号：US07205571B2

公开(公告)日：2007-04-17

申请号：US10963599

申请日：2004-10-14

申请人： Byung Chul Ahn ,  Soon Sung Yoo ,  Heung Lyul Cho

发明人： Byung Chul Ahn ,  Soon Sung Yoo ,  Heung Lyul Cho

IPC分类号： H01L29/15 ,  G02F1/1365

CPC分类号： G02F1/136227 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A thin film transistor (TFT) substrate is fabricated in three mask processes. In a first mask process, a gate line and a gate electrode are formed. In a second mask process, a data line, a source electrode, a drain electrode, a semiconductor layer, and a first upper storage electrode overlapping the gate line are formed from a gate insulating film, undoped and doped amorphous silicon layers, and a data metal layer. In a third mask process, a pixel hole is formed through protective and gate insulating films within and outside a pixel area, the first upper storage electrode is partially removed, a pixel electrode contacts a side of the drain electrode within the pixel hole at the pixel area, and a second upper storage electrode contacts a side of the first upper storage electrode in the pixel hole outside the pixel area.

公开(公告)号：US07078279B2

公开(公告)日：2006-07-18

申请号：US10950493

申请日：2004-09-28

申请人： Soon Sung Yoo ,  Heung Lyul Cho

发明人： Soon Sung Yoo ,  Heung Lyul Cho

IPC分类号： H01L21/336 ,  H01L29/41 ,  G02F1/1343

CPC分类号： G02F1/13458 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2201/50 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  Y10S438/951

摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate includes involves a three-round mask process, which includes: forming a gate pattern on a substrate; forming a gate insulating film on the substrate having the gate pattern thereon; forming a source/drain pattern and a semiconductor pattern; forming a passivation film to protect the thin film transistor on an entire surface of the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern; and forming a transparent electrode pattern being extended from a lateral surface of the passivation film pattern and formed at an area except for the passivation film pattern.

摘要翻译： 公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。 制造薄膜晶体管阵列基板的方法包括三向掩模工艺，其包括：在基板上形成栅极图案; 在其上具有栅极图案的衬底上形成栅极绝缘膜; 形成源极/漏极图案和半导体图案; 形成钝化膜，以在衬底的整个表面上保护薄膜晶体管; 在钝化膜上形成光刻胶图案; 使用光致抗蚀剂图案来图案化钝化膜以形成钝化膜图案; 以及形成从钝化膜图案的侧表面延伸并形成在除了钝化膜图案之外的区域的透明电极图案。

公开(公告)号：US07001796B2

公开(公告)日：2006-02-21

申请号：US10875318

申请日：2004-06-25

申请人： Heung Lyul Cho ,  Seung Hee Nam ,  Jae Young Oh

发明人： Heung Lyul Cho ,  Seung Hee Nam ,  Jae Young Oh

IPC分类号： H01C21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124

摘要： An array substrate of a liquid crystal display (LCD) device and a method for fabricating the same is disclosed, to decrease the unit cost and time of fabrication by decreasing the usage count of mask, which includes simultaneously forming a gate line, a gate electrode and a pixel electrode on a substrate; depositing a gate insulating layer and an active layer on an entire surface of the substrate including the gate line; patterning the gate insulating layer and the active layer to remain on the gate line and the gate electrode; selectively removing the active layer above the gate line; forming a data line perpendicular to the gate line and source/drain electrodes; and depositing a passivation layer on the entire surface of the substrate including the data line.

摘要翻译： 公开了一种液晶显示器（LCD）器件的阵列基板及其制造方法，通过减少包括同时形成栅极线的掩模的使用次数来减小制造的单位成本和时间，栅电极 和基板上的像素电极; 在包括栅极线的基板的整个表面上沉积栅极绝缘层和有源层; 图案化栅极绝缘层和有源层以保留在栅极线和栅电极上; 选择性地去除栅极线上方的有源层; 形成垂直于栅极线和源极/漏极的数据线; 以及在包括所述数据线的所述衬底的整个表面上沉积钝化层。

公开(公告)号：US20100326469A1

公开(公告)日：2010-12-30

申请号：US12880761

申请日：2010-09-13

申请人： Oh Nam Kwon ,  Heung Lyul Cho

发明人： Oh Nam Kwon ,  Heung Lyul Cho

IPC分类号： B08B1/00 ,  B08B3/00

CPC分类号： G03F7/422 ,  H01L27/1214 ,  H01L27/1288

摘要： The present invention relates to an apparatus and a method of fabricating a thin film transistor array substrate. The apparatus includes a dip strip part for stripping a photo-resist pattern and a thin film formed on a substrate by using a stripper; a removing part for removing residual photo-resist and thin film from the substrate; and a jet strip part for jetting the stripper to remove residual particles of photo-resist and thin film left on the substrate. The method of fabricating includes dipping a substrate in a stripper, wherein the substrate has a photo-resist pattern and a thin film, the thin film being formed on an entire surface of the substrate so as to cover the photo-resist pattern; removing residual photo-resist and thin film using the stripper; and removing particles of residual photo-resist and thin film left on the substrate.

摘要翻译： 本发明涉及一种制造薄膜晶体管阵列基板的装置和方法。 该装置包括用于剥离光致抗蚀剂图案的浸渍条部分和通过使用剥离剂在基底上形成的薄膜; 用于从基板去除残留的光致抗蚀剂和薄膜的去除部分; 以及用于喷射剥离剂以除去留在基材上的残留的光致抗蚀剂和薄膜的喷射条部分。 制造方法包括将基板浸渍在剥离器中，其中所述基板具有光刻胶图案和薄膜，所述薄膜形成在所述基板的整个表面上以覆盖所述光刻胶图案; 使用剥离剂除去残留的光致抗蚀剂和薄膜; 并去除留在基板上的残留光致抗蚀剂和薄膜的颗粒。

公开(公告)号：US07807339B2

公开(公告)日：2010-10-05

申请号：US11314313

申请日：2005-12-22

申请人： Oh Nam Kwon ,  Heung Lyul Cho

发明人： Oh Nam Kwon ,  Heung Lyul Cho

IPC分类号： G03F1/00 ,  G03F7/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0007

摘要： A patterning method includes depositing a pattern target layer on a surface of a substrate, providing a printing plate with concaves in a first side of a transparent substrate and an opaque layer on the first side except in the concaves of the first sides, filling resins into the concaves of the printing plate, positioning the substrate of the printing plate to correspond to an upper portion of the pattern target layer, and transferring resins of the printing plate onto the pattern target layer by exposing resins to a curing light to harden resins.

摘要翻译： 图案化方法包括在基板的表面上沉积图案目标层，在透明基板的第一侧提供具有凹陷的印刷版，并且在第一侧的凹部之外的第一侧上设置不透明层，将树脂填充到 印版的凹部，将印版的基板定位成对应于图案目标层的上部，并且通过将树脂暴露于固化光以使树脂硬化来将印刷板的树脂转印到图案目标层上。

公开(公告)号：US07023017B2

公开(公告)日：2006-04-04

申请号：US10979096

申请日：2004-11-02

申请人： Byung Chul Ahn ,  Oh Nam Kwon ,  Heung Lyul Cho

发明人： Byung Chul Ahn ,  Oh Nam Kwon ,  Heung Lyul Cho

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G02F1/134363 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/1288

摘要： A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetween to define a pixel area; a second common line crossing the first common line having the gate insulating film therebetween; a thin film transistor connected to the gate line and the data line; a common electrode extending from the second common line in said pixel area; a pixel electrode that is parallel to the common electrode and the second common line; a protective film for covering the thin film transistor; a gate pad having a lower gate pad electrode connected to an upper gate pad electrode through a first contact hole; a common pad having a lower common pad electrode connected to an upper common pad electrode through a second contact hole; and a data pad having a lower data pad electrode connected to an upper data pad electrode provided within a third contact hole.

公开(公告)号：US06818923B2

公开(公告)日：2004-11-16

申请号：US10273891

申请日：2002-10-21

申请人： Woong Kwon Kim ,  Heung Lyul Cho ,  Seung Hee Nam

发明人： Woong Kwon Kim ,  Heung Lyul Cho ,  Seung Hee Nam

IPC分类号： H01L29786

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F2001/136236 ,  H01L27/1255 ,  H01L27/1288

摘要： A thin film transistor array substrate, and its manufacturing method, that is made using a three-round mask process. Gate patterns, each of which includes a gate line consisting of a transparent metal pattern and a gate metal pattern, a gate electrode, a lower gate pad, a lower data pad, and a pixel electrode are formed using a first mask process. A second mask process forms a gate insulating pattern and a semiconductor pattern. A third mask process forms source and drain patterns, each of which includes a data line, a source electrode, a drain electrode, an upper gate pad and an upper data pad. Additionally, the gate metal pattern on an upper portion of the pixel electrode is removed.

摘要翻译： 一种薄膜晶体管阵列基板及其制造方法，采用三面掩模工艺制成。 使用第一掩模处理形成栅极图案，每个栅极图案包括由透明金属图案和栅极金属图案构成的栅极线，栅电极，下栅极焊盘，下数据焊盘和像素电极。 第二掩模工艺形成栅极绝缘图案和半导体图案。 第三掩模处理形成源极和漏极图案，其中每个包括数据线，源电极，漏电极，上栅极焊盘和上数据焊盘。 此外，去除像素电极上部的栅极金属图案。