公开(公告)号：US20130244437A1

公开(公告)日：2013-09-19

申请号：US13421069

申请日：2012-03-15

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/28132 ,  H01L21/3088

摘要： One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.

摘要翻译： 本文公开的一种说明性方法包括在结构之上形成牺牲心轴，在牺牲心轴的相对侧上形成多个第一侧壁间隔物，去除牺牲心轴，在第一侧壁中的每一个的相对侧上形成多个第二侧壁间隔 并且移除第一侧壁间隔物，从而限定由多个第二侧壁间隔件组成的图案化间隔物掩模层。

公开(公告)号：US20130175545A1

公开(公告)日：2013-07-11

申请号：US13345457

申请日：2012-01-06

申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC分类号： H01L29/161 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.

摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。

公开(公告)号：US08476131B2

公开(公告)日：2013-07-02

申请号：US13216791

申请日：2011-08-24

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Ricardo P. Mikalo

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Ricardo P. Mikalo

IPC分类号： H01L21/8238 ,  H01L21/331

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.

摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。

公开(公告)号：US20130052819A1

公开(公告)日：2013-02-28

申请号：US13218089

申请日：2011-08-25

申请人： Thilo Scheiper ,  Peter Javorka ,  Stefan Flachowsky ,  Clemens Fitz

发明人： Thilo Scheiper ,  Peter Javorka ,  Stefan Flachowsky ,  Clemens Fitz

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices by using different temperatures during the silicidation processes. In one example, the method includes forming a plurality of N-doped source/drain regions and a plurality of P-doped source/drain regions in a semiconducting substrate and performing a first heating process at a first temperature to initially form a first metal silicide region in each of the P-doped source/drain regions. The method further includes performing a second heating process at a second temperature to initially form a second metal silicide region in each of the N-doped source/drain regions, wherein the second temperature is less than the first temperature and performing a third heating process at a third temperature to complete the formation of the first and second metal silicide regions, wherein the third temperature is greater than the first temperature.

摘要翻译： 本文公开了通过在硅化工艺期间使用不同温度在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个N掺杂源极/漏极区域和多个P掺杂的源极/漏极区域，并且在第一温度下执行第一加热过程以最初形成第一金属硅化物 每个P掺杂源/漏区中的区域。 该方法还包括在第二温度下执行第二加热处理，以在N掺杂源极/漏极区域中的每一个中初始形成第二金属硅化物区域，其中第二温度小于第一温度，并且在 第三温度以完成所述第一和第二金属硅化物区域的形成，其中所述第三温度大于所述第一温度。

公开(公告)号：US20130052783A1

公开(公告)日：2013-02-28

申请号：US13216921

申请日：2011-08-24

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/26526 ,  H01L29/7848

摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.

摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。

公开(公告)号：US20130049128A1

公开(公告)日：2013-02-28

申请号：US13217975

申请日：2011-08-25

申请人： Thilo Scheiper ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.

摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 在一个示例中，该器件包括栅电极和形成在靠近栅电极结构的衬底中的多个源/漏区。 该器件还包括形成在每个源极/漏极区域中的第一金属硅化物区域，其中第一金属硅化物区域具有形成在每个源极/漏极区域中的内部边界和第二金属硅化物区域，其中第二金属硅化物 区域横向位于第一金属硅化物区域的内边界和栅电极结构的边缘之间。

公开(公告)号：US20120153399A1

公开(公告)日：2012-06-21

申请号：US13192620

申请日：2011-07-28

申请人： Jan Hoentschel ,  Stefan Flachowsky ,  Steven Langdon ,  Thilo Scheiper

发明人： Jan Hoentschel ,  Stefan Flachowsky ,  Steven Langdon ,  Thilo Scheiper

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.

摘要翻译： 漏极和源极区域可以至少部分地由原位掺杂的外延生长的半导体材料形成，用于为低功率和高性能应用设计的复杂半导体器件中的互补晶体管。 为此，空穴可以用原位掺杂的半导体材料重新填充，在一些说明性实施例中，还可以在互补晶体管的沟道区域中提供期望的应变。

公开(公告)号：US09224840B2

公开(公告)日：2015-12-29

申请号：US13545597

申请日：2012-07-10

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC分类号： H01L27/088 ,  H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7851

摘要： A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space.

摘要翻译： 公开了一种利用覆盖多个翅片结构的虚拟栅极结构在替代栅极工艺流程中制造集成电路的方法。 该方法包括去除伪栅极结构以形成第一空隙空间，沉积成形材料以填充第一空隙空间，去除多个翅片结构的一部分以形成第二空隙空间，外延生长高载流子迁移率材料 以填充第二空隙空间，移除整形材料以形成第三空隙空间，以及沉积更换的金属栅极材料以填充第三空隙空间。

公开(公告)号：US08941187B2

公开(公告)日：2015-01-27

申请号：US13349942

申请日：2012-01-13

申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC分类号： H01L27/088

CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

摘要： In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

摘要翻译： 在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。 在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

公开(公告)号：US08753969B2

公开(公告)日：2014-06-17

申请号：US13343513

申请日：2012-01-27

申请人： Stefan Flachowsky ,  Ralf Illgen

发明人： Stefan Flachowsky ,  Ralf Illgen

IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.

摘要翻译： 提供了MOS器件及其制造方法。 在一个实施例中，MOS器件制造在半导体衬底上和半导体衬底内。 该方法包括形成具有顶部和侧壁并且具有覆盖半导体衬底的栅极绝缘体的栅极结构，覆盖栅极绝缘体的栅电极和覆盖栅电极的盖。 氧化物衬垫沉积在栅极结构的顶部和侧壁上。 在该方法中，从栅极结构中蚀刻盖，露出从栅极结构向上延伸的氧化物针。 应力诱导层沉积在氧化物针和栅极结构上，半导体衬底被退火。 然后，去除应力诱导衬垫。