-
1.发明申请Methods of Forming a Semiconductor Device with Recessed Source/Drain Regions, and a Semiconductor Device Comprising Same 有权形成具有嵌入式源极/漏极区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US20130049126A1
公开(公告)日：2013-02-28
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
-
2.发明授权Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same 有权形成具有凹陷源/设计区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US08476131B2
公开(公告)日：2013-07-02
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
-
3.发明申请Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers 审中-公开使用减少的间隔物形成高度缩放的半导体器件的方法公开(公告)号：US20130065367A1
公开(公告)日：2013-03-14
申请号：US13231470
申请日：2011-09-13
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864
摘要： In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.
摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在形成第一间隔物之后，形成用于PMOS晶体管和用于NMOS晶体管的栅电极结构，形成靠近栅电极结构的第一间隔，在衬底中形成延伸注入区 晶体管和形成延伸注入区之后，形成靠近PMOS晶体管的第一间隔物的第二隔离层。 该方法还包括执行蚀刻工艺，其中第二间隔件就位以在衬底附近限定用于PMOS晶体管的栅极结构附近的多个空腔，去除第一和第二间隔物，形成邻近两个栅电极结构的第三间隔物 的晶体管，并且在用于晶体管的衬底中形成深源极/漏极注入区域。
-
4.发明申请Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts 审中-公开形成器件级导电触点以提高器件性能的方法和包括这种触点的半导体器件公开(公告)号：US20130207275A1
公开(公告)日：2013-08-15
申请号：US13397199
申请日：2012-02-15
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/1306 , H01L2924/00 , H01L2924/13091
摘要： Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.
摘要翻译： 本文公开了形成器件级导电触点以改善器件性能的各种方法以及具有这种改进的触发电平触点配置的各种半导体器件。 在一个示例中，本文公开的装置包括定位在第一绝缘材料层中的第一器件级导电触点，其中第一器件级导电触点导电耦合到半导体器件，第二器件级导电触点位于上方并导电耦合 到所述第一器件级触点，其中所述第二器件级触点定位在第二绝缘材料层中，以及用于所述器件的第一布线层，所述第一布线层位于所述第二器件级导电触点的上方并与其导电耦合。
-
5.发明授权公开(公告)号：US08536034B2
公开(公告)日：2013-09-17
申请号：US13216921
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26526 , H01L29/7848
摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。
-
6.发明申请METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE 审中-公开使用新型化合物边框转印技术在集成电路产品上形成特征的方法公开(公告)号：US20130244437A1
公开(公告)日：2013-09-19
申请号：US13421069
申请日：2012-03-15
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/28132 , H01L21/3088
摘要： One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.
摘要翻译： 本文公开的一种说明性方法包括在结构之上形成牺牲心轴，在牺牲心轴的相对侧上形成多个第一侧壁间隔物，去除牺牲心轴，在第一侧壁中的每一个的相对侧上形成多个第二侧壁间隔 并且移除第一侧壁间隔物，从而限定由多个第二侧壁间隔件组成的图案化间隔物掩模层。
-
7.发明申请公开(公告)号：US20130052783A1
公开(公告)日：2013-02-28
申请号：US13216921
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/26526 , H01L29/7848
摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。
-
公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
-
公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
-
10.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS 有权用于制造具有基板接触的集成电路的方法和具有基板接触的集成电路公开(公告)号：US20130256901A1
公开(公告)日：2013-10-03
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
-
-
-
-
-
-
-
-
-
搜索结果
136 条记录 (耗时 0.02 秒)
