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    Threshold Voltage Adjustment in a Fin Transistor by Corner Implantation
    1.
    发明申请
    Threshold Voltage Adjustment in a Fin Transistor by Corner Implantation 有权
    通过角植入在翅片晶体管中的阈值电压调整

    公开(公告)号：US20130049121A1

    公开(公告)日：2013-02-28

    申请号：US13217009

    申请日：2011-08-24

    申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    摘要翻译： 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可能有意地降低多个栅极晶体管的阈值电压特性，从而获得阈值 多个栅极晶体管和平面晶体管的电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    Strain engineering in three-dimensional transistors based on strained isolation material
    2.
    发明授权
    Strain engineering in three-dimensional transistors based on strained isolation material 有权
    基于应变隔离材料的三维晶体管中的应变工程

    公开(公告)号：US08941187B2

    公开(公告)日：2015-01-27

    申请号：US13349942

    申请日：2012-01-13

    申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L27/088

    CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

    摘要： In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

    摘要翻译： 在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。 在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

    Threshold voltage adjustment in a Fin transistor by corner implantation
    3.
    发明授权
    Threshold voltage adjustment in a Fin transistor by corner implantation 有权
    通过角落植入在Fin晶体管中的阈值电压调节

    公开(公告)号：US08580643B2

    公开(公告)日：2013-11-12

    申请号：US13217009

    申请日：2011-08-24

    申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    摘要翻译： 当在共同制造顺序中形成复杂的多个栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material
    4.
    发明申请
    Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material 有权
    基于应变隔离材料的三维晶体管中的应变工程

    公开(公告)号：US20130181299A1

    公开(公告)日：2013-07-18

    申请号：US13349942

    申请日：2012-01-13

    申请人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

    摘要： In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.

    摘要翻译： 在三维晶体管配置中，至少在漏极和源极区域中提供应变诱导隔离材料，从而引起应变，特别是在三维晶体管的PN结处和附近。 在这种情况下，可以实现卓越的晶体管性能，而在一些说明性实施例中，甚至相同类型的内部应力隔离材料也可能导致P沟道晶体管和N沟道晶体管的优异的晶体管性能。

    In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
    7.
    发明授权
    In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices 有权
    在PMOS和NMOS器件中嵌入的应力区域的原位掺杂和无扩散退火

    公开(公告)号：US09012277B2

    公开(公告)日：2015-04-21

    申请号：US13346043

    申请日：2012-01-09

    申请人： Stefan Flachowsky ,  Ralf Illgen

    发明人： Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L21/36 ,  H01L21/268 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    CPC分类号： H01L21/823807 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.

    摘要翻译： 通常，本公开涉及使用原位掺杂和基本上无扩散退火技术在诸如晶体管元件等的半导体器件中形成双嵌入应力源区域的方法。 本文公开的一种说明性方法包括分别在半导体衬底的PMOS和NMOS器件区域中形成第一和第二空腔，然后执行第一和第二外延沉积工艺，以在第一和第二外延材料区域中形成第一和第二外延材料区域 腔。 该方法还包括执行单一热处理工艺以激活原位掺杂的第一和第二嵌入材料区域中的掺杂剂。

    Methods of Forming a Semiconductor Device with Recessed Source/Drain Regions, and a Semiconductor Device Comprising Same
    8.
    发明申请
    Methods of Forming a Semiconductor Device with Recessed Source/Drain Regions, and a Semiconductor Device Comprising Same 有权
    形成具有嵌入式源极/漏极区域的半导体器件的方法以及包括其的半导体器件

    公开(公告)号：US20130049126A1

    公开(公告)日：2013-02-28

    申请号：US13216791

    申请日：2011-08-24

    申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Ricardo P. Mikalo

    发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Ricardo P. Mikalo

    IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814

    摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.

    摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。

    Replacement gate FinFET structures with high mobility channel
    9.
    发明授权
    Replacement gate FinFET structures with high mobility channel 有权
    具有高迁移率通道的替代栅极FinFET结构

    公开(公告)号：US09224840B2

    公开(公告)日：2015-12-29

    申请号：US13545597

    申请日：2012-07-10

    申请人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

    IPC分类号： H01L27/088 ,  H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7851

    摘要： A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space.

    摘要翻译： 公开了一种利用覆盖多个翅片结构的虚拟栅极结构在替代栅极工艺流程中制造集成电路的方法。 该方法包括去除伪栅极结构以形成第一空隙空间，沉积成形材料以填充第一空隙空间，去除多个翅片结构的一部分以形成第二空隙空间，外延生长高载流子迁移率材料 以填充第二空隙空间，移除整形材料以形成第三空隙空间，以及沉积更换的金属栅极材料以填充第三空隙空间。

    Methods for fabricating MOS devices with stress memorization
    10.
    发明授权
    Methods for fabricating MOS devices with stress memorization 有权
    用于制造具有应力记忆的MOS器件的方法

    公开(公告)号：US08753969B2

    公开(公告)日：2014-06-17

    申请号：US13343513

    申请日：2012-01-27

    申请人： Stefan Flachowsky ,  Ralf Illgen

    发明人： Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

    摘要： A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.

    摘要翻译： 提供了MOS器件及其制造方法。 在一个实施例中，MOS器件制造在半导体衬底上和半导体衬底内。 该方法包括形成具有顶部和侧壁并且具有覆盖半导体衬底的栅极绝缘体的栅极结构，覆盖栅极绝缘体的栅电极和覆盖栅电极的盖。 氧化物衬垫沉积在栅极结构的顶部和侧壁上。 在该方法中，从栅极结构中蚀刻盖，露出从栅极结构向上延伸的氧化物针。 应力诱导层沉积在氧化物针和栅极结构上，半导体衬底被退火。 然后，去除应力诱导衬垫。