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1.发明申请Methods of Forming a Semiconductor Device with Recessed Source/Drain Regions, and a Semiconductor Device Comprising Same 有权形成具有嵌入式源极/漏极区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US20130049126A1
公开(公告)日：2013-02-28
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
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2.发明授权Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same 有权形成具有凹陷源/设计区域的半导体器件的方法以及包括其的半导体器件公开(公告)号：US08476131B2
公开(公告)日：2013-07-02
申请号：US13216791
申请日：2011-08-24
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823807 , H01L21/823814
摘要： In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
摘要翻译： 在一个示例中，本文公开的方法包括形成用于PMOS晶体管的栅电极结构和用于NMOS晶体管的栅电极结构，在靠近PMOS晶体管的栅电极结构的基板中形成多个空腔，并执行外延沉积 形成凸起的硅 - 锗区域的过程是空腔。 该方法的结论是在PMOS晶体管和NMOS晶体管上执行公共蚀刻工艺以在NMOS晶体管的栅极电极结构附近限定衬底中的凹陷区域，并且减少位于该晶体管上方的硅 - 锗材料的量 用于PMOS晶体管的衬底的表面。
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3.发明申请Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts 审中-公开形成器件级导电触点以提高器件性能的方法和包括这种触点的半导体器件公开(公告)号：US20130207275A1
公开(公告)日：2013-08-15
申请号：US13397199
申请日：2012-02-15
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/1306 , H01L2924/00 , H01L2924/13091
摘要： Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.
摘要翻译： 本文公开了形成器件级导电触点以改善器件性能的各种方法以及具有这种改进的触发电平触点配置的各种半导体器件。 在一个示例中，本文公开的装置包括定位在第一绝缘材料层中的第一器件级导电触点，其中第一器件级导电触点导电耦合到半导体器件，第二器件级导电触点位于上方并导电耦合 到所述第一器件级触点，其中所述第二器件级触点定位在第二绝缘材料层中，以及用于所述器件的第一布线层，所述第一布线层位于所述第二器件级导电触点的上方并与其导电耦合。
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4.发明申请Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers 审中-公开使用减少的间隔物形成高度缩放的半导体器件的方法公开(公告)号：US20130065367A1
公开(公告)日：2013-03-14
申请号：US13231470
申请日：2011-09-13
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864
摘要： In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.
摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在形成第一间隔物之后，形成用于PMOS晶体管和用于NMOS晶体管的栅电极结构，形成靠近栅电极结构的第一间隔，在衬底中形成延伸注入区 晶体管和形成延伸注入区之后，形成靠近PMOS晶体管的第一间隔物的第二隔离层。 该方法还包括执行蚀刻工艺，其中第二间隔件就位以在衬底附近限定用于PMOS晶体管的栅极结构附近的多个空腔，去除第一和第二间隔物，形成邻近两个栅电极结构的第三间隔物 的晶体管，并且在用于晶体管的衬底中形成深源极/漏极注入区域。
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5.发明授权公开(公告)号：US08536034B2
公开(公告)日：2013-09-17
申请号：US13216921
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26526 , H01L29/7848
摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。
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6.发明申请METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE 审中-公开使用新型化合物边框转印技术在集成电路产品上形成特征的方法公开(公告)号：US20130244437A1
公开(公告)日：2013-09-19
申请号：US13421069
申请日：2012-03-15
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/28132 , H01L21/3088
摘要： One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.
摘要翻译： 本文公开的一种说明性方法包括在结构之上形成牺牲心轴，在牺牲心轴的相对侧上形成多个第一侧壁间隔物，去除牺牲心轴，在第一侧壁中的每一个的相对侧上形成多个第二侧壁间隔 并且移除第一侧壁间隔物，从而限定由多个第二侧壁间隔件组成的图案化间隔物掩模层。
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7.发明申请公开(公告)号：US20130052783A1
公开(公告)日：2013-02-28
申请号：US13216921
申请日：2011-08-24
申请人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
发明人： Stefan Flachowsky , Ralf Illgen , Thilo Scheiper , Jan Hoentschel
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/26526 , H01L29/7848
摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。
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8.发明授权Methods for the fabrication of integrated circuits including back-etching of raised conductive structures 有权用于制造包括凸起导电结构的背蚀刻的集成电路的方法公开(公告)号：US08524566B2
公开(公告)日：2013-09-03
申请号：US13331951
申请日：2011-12-20
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823425
摘要： Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.
摘要翻译： 提供了一种用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件，其包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域和沟道区域上的栅极堆叠。 在至少一个S / D区域上形成至少一个凸起的导电结构，并且通过横向间隙与栅极堆叠分离。 然后，升高的导电结构被反蚀刻以增加横向间隙的宽度，并且在完成的半导体器件的操作期间减小凸起的导电结构和栅极堆叠之间的寄生边缘电容。
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公开(公告)号：US20130183817A1
公开(公告)日：2013-07-18
申请号：US13350891
申请日：2012-01-16
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/2686 , H01L21/28176 , H01L21/31155 , H01L29/512 , H01L29/66545
摘要： Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
摘要翻译： 这里公开了减少诸如晶体管的半导体器件中的栅极泄漏的各种方法。 在一个示例中，本文公开的方法包括执行蚀刻工艺以限定晶体管的栅极绝缘层，其中栅极绝缘层具有蚀刻边缘，执行成角度的离子注入工艺以将离子注入靠近蚀刻的栅极绝缘层 并且在进行成角度的离子注入工艺之后进行退火处理。
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10.发明授权Fabrication of a semiconductor device with extended epitaxial semiconductor regions 有权具有扩展外延半导体区域的半导体器件的制造公开(公告)号：US08642420B2
公开(公告)日：2014-02-04
申请号：US13219331
申请日：2011-08-26
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： A method of fabricating a semiconductor device structure begins by forming a layer of oxide material overlying a first gate structure having a first silicon nitride cap and overlying a second gate structure having a second silicon nitride cap. The first gate structure corresponds to a p-type transistor to be fabricated, and the second gate structure corresponds to an n-type transistor to be fabricated. The method continues by performing a tilted ion implantation procedure to implant ions of an impurity species in a channel region of semiconductor material underlying the first gate structure, during which an ion implantation mask protects the second gate structure. Thereafter, the ion implantation mask and the layer of oxide material are removed, and regions of epitaxial semiconductor material are formed corresponding to source and drain regions for the first gate structure. Thereafter, the first silicon nitride cap and the second silicon nitride cap are removed.
摘要翻译： 制造半导体器件结构的方法开始于形成覆盖具有第一氮化硅帽的第一栅极结构的氧化物层，并且覆盖具有第二氮化硅帽的第二栅极结构。 第一栅极结构对应于要制造的p型晶体管，并且第二栅极结构对应于待制造的n型晶体管。 该方法通过执行倾斜离子注入程序来将杂质物质的离子注入到第一栅极结构下面的半导体材料的沟道区域中，在此期间离子注入掩模保护第二栅极结构。 此后，去除离子注入掩模和氧化物层，并且对应于第一栅极结构的源区和漏区形成外延半导体材料的区域。 此后，去除第一氮化硅盖和第二氮化硅盖。
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