公开(公告)号：US08891266B2

公开(公告)日：2014-11-18

申请号：US13418921

申请日：2012-03-13

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H02M7/00 ,  H02M7/06

CPC分类号： H02M7/106 ,  H01L21/304 ,  H01L21/6835 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/872 ,  H01L2221/6835 ,  H01L2221/68368 ,  Y02B70/1483

摘要： High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier.

摘要翻译： 高压二极管连接的氮化镓高电子迁移率晶体管结构或肖特基二极管用于包括固态高分子电压倍增器的高k介质电容器的网络中。 由氮化镓中的垂直p / n结形成的超结，有利于高电子迁移率晶体管结构和肖特基二极管的工作。 用于设计，测试或制造集成电路的设计结构被有形地体现在机器可读介质中并且包括固态电压倍增器的元件。

公开(公告)号：US08809168B2

公开(公告)日：2014-08-19

申请号：US13037944

申请日：2011-03-01

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/20 ,  H01L29/02

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.

摘要翻译： 使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。 在这样的生长过程中氢稀释可以变化以提供应变梯度。

公开(公告)号：US20130240893A1

公开(公告)日：2013-09-19

申请号：US13418476

申请日：2012-03-13

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L27/088 ,  G06F17/50

CPC分类号： H01L29/7786 ,  G06F17/5045 ,  G06F17/5063 ,  H01L21/6835 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/872 ,  H01L2221/68363

摘要： A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both n-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

摘要翻译： 电路包括具有栅极的第一场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子; 以及具有栅极的第二场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子。 第二场效应晶体管和第一场效应晶体管是相同类型的，即n沟道晶体管或两个p沟道晶体管。 第一场效应晶体管的第二漏极 - 源极端子耦合到第二场效应晶体管的第一漏极 - 源极端子; 并且第二场效应晶体管的栅极耦合到第二场效应晶体管的第一漏极 - 源极端子。 所得到的三端子器件可以替代否则在所提出的工作条件下会损坏的单个场效应晶体管。

公开(公告)号：US20130014811A1

公开(公告)日：2013-01-17

申请号：US13179731

申请日：2011-07-11

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/06 ,  H01L31/0304

CPC分类号： H01L31/075 ,  H01L31/03046 ,  H01L31/074 ,  Y02E10/544 ,  Y02P70/521

摘要： An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

摘要翻译： 在III-V基极和异质结III-V族太阳能电池结构的本征非晶半导体层之间提供In x Ga 1-x As夹层。 可以通过在结构内并入中间层来获得改进的表面钝化和开路电压。

公开(公告)号：US08748296B2

公开(公告)日：2014-06-10

申请号：US13172793

申请日：2011-06-29

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

IPC分类号： H01L21/00

CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

公开(公告)号：US20130082357A1

公开(公告)日：2013-04-04

申请号：US13253059

申请日：2011-10-04

申请人： Ibrahim Alhomoudi ,  Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

发明人： Ibrahim Alhomoudi ,  Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC分类号： H01L29/16 ,  H01L29/04 ,  H01L21/60

CPC分类号： H01L31/02363 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/03682 ,  Y02E10/544 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture.

摘要翻译： 半导体材料的基层由天然纹理表面形成。 基底层可以结合在光伏结构内。 使用受控的剥落技术，其中衬底断裂沿所选方向传播以引起小平面的形成。 （001）硅衬底的[110]方向剥落导致所得到的基底层的这种面的形成，提供了自然的表面纹理。

公开(公告)号：US20130005116A1

公开(公告)日：2013-01-03

申请号：US13172793

申请日：2011-06-29

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

IPC分类号： H01L21/301

CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

公开(公告)号：US20120322230A1

公开(公告)日：2012-12-20

申请号：US13159877

申请日：2011-06-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC分类号： H01L21/78

CPC分类号： H01L21/7813 ,  H01L21/304

摘要： The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.

摘要翻译： 本公开提供了从单个基底基板开始形成两个器件晶片的方法。 该方法包括首先提供一种结构，该结构包括具有位于基底板的最上表面和最底表面之上或之内的器件层的基底基板。 基底可以具有双面抛光表面。 包括器件层的结构在基底衬底内位于器件层之间的区域中被剥落。 剥落提供了包括基底部分的一部分和器件层之一的第一器件晶片，以及包括基底衬底的另一部分和器件层另一部分的第二器件晶片。

公开(公告)号：US20130316538A1

公开(公告)日：2013-11-28

申请号：US13478749

申请日：2012-05-23

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Augustin J. Hong ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Kuen-Ting Shiu

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Augustin J. Hong ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Davood Shahrjerdi ,  Kuen-Ting Shiu

IPC分类号： H01L21/304 ,  H01L21/306

CPC分类号： H01L21/304 ,  H01L31/02363 ,  Y02E10/50

摘要： The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns.

摘要翻译： 在本公开中实现表面图案的产生或表面图案的复制，而不需要采用蚀刻工艺。 相反，在本公开中使用称为剥落的独特的断裂模式来生成或复制表面图案。 在表面图案生成的情况下，在应力层中设置表面图案，然后进行剥离。 在表面图案复制的情况下，在基底表面上或表面上形成表面图案，然后施加应力层。 施加应力层后，进行剥落。 利用剥落产生或复制表面图案为生成或复制表面图案提供了低成本的手段。

公开(公告)号：US08841203B2

公开(公告)日：2014-09-23

申请号：US13159877

申请日：2011-06-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/762

CPC分类号： H01L21/7813 ,  H01L21/304

摘要： The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.

摘要翻译： 本公开提供了从单个基底基板开始形成两个器件晶片的方法。 该方法包括首先提供一种结构，该结构包括具有位于基底板的最上表面和最底表面之上或之内的器件层的基底基板。 基底可以具有双面抛光表面。 包括器件层的结构在基底衬底内位于器件层之间的区域中被剥落。 剥落提供了包括基底部分的一部分和器件层之一的第一器件晶片，以及包括基底衬底的另一部分和器件层另一部分的第二器件晶片。