公开(公告)号：US20050250332A1

公开(公告)日：2005-11-10

申请号：US10840049

申请日：2004-05-05

申请人： Boq-Kang Hwu ,  Chung-Shi Liu ,  Chen-Hua Yu

发明人： Boq-Kang Hwu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L21/321 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/76838 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873

摘要： A method for reducing or preventing contamination or oxidation of copper surfaces included in semiconductor process wafers including providing a semiconductor wafer including copper features having newly formed process surfaces following a semiconductor manufacturing process forming the newly formed process surfaces; exposing the process surfaces to an alkaline solution for a period of time sufficient to chemically modify the newly formed process surfaces prior to substantial exposure of the process surfaces to a contaminating or oxidizing atmosphere; and, placing the semiconductor wafer in a semiconductor wafer holding environment in queue for subsequent semiconductor manufacturing processes.

摘要翻译： 一种用于减少或防止包含在半导体工艺晶片中的铜表面的污染或氧化的方法，包括：提供包含具有新形成的工艺表面的铜特征的半导体晶片; 将工艺表面暴露于碱性溶液一段足以在将工艺表面大量暴露于污染或氧化气氛之前化学改性新形成的工艺表面的时间; 并且将半导体晶片置于半导体晶片保持环境中，用于随后的半导体制造工艺。

公开(公告)号：US06703286B1

公开(公告)日：2004-03-09

申请号：US09354854

申请日：1999-07-29

申请人： Chen-Hua Yu ,  Chung-Shi Liu

发明人： Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L2176

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method is provided whereby successive layers of bond pads can be created. A pattern is created in the preceding level of metal bond pad, a dielectric is deposited over this pattern, openings are created in the dielectric that match the pattern, an opening is created above this pattern and metal is deposited inside this opening creating a square metal bond pad that is joined to the pattern that has been created in the metal of the preceding bond pad.

摘要翻译： 提供了一种可以产生连续的接合层的层的方法。 在金属接合焊盘的先前水平上形成图案，在该图案上沉积电介质，在电介质中形成与图案匹配的开口，在该图案之上形成开口，并且金属沉积在该开口内部，形成方形金属 接合焊盘，其连接到在先前接合焊盘的金属中已经形成的图案。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

公开(公告)号：US06287961B1

公开(公告)日：2001-09-11

申请号：US09225380

申请日：1999-01-04

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31138 ,  H01L21/3127 ,  H01L21/76825 ,  H01L2221/1031 ,  H01L2221/1036 ,  Y10S438/924

摘要： A method for forming through a dielectric layer a trench contiguous with a via. There is provided a substrate having a contact region formed therein. There is then formed upon the substrate a patterned first dielectric layer defining a via accessing the contact region, where the patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed completely covering the patterned first dielectric layer and filling the via a the blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket hard mask layer a patterned photoresist layer which provides an exposed portion of the blanket hard mask layer greater that an areal dimension of the via and at least partially overlapping the areal dimension of the via. There is then implanted into the exposed portion of the blanket hard mask layer and into a portion of the blanket second dielectric layer aligned beneath the exposed portion of the blanket hard mask layer a dose of an ion to form an ion implanted portion of the blanket hard mask layer and an ion implanted portion of the blanket second dielectric layer, where the ion implanted portion of the blanket second dielectric layer has an enhanced etch rate within the oxygen containing plasma in comparison with a non ion implanted portion of the blanket second dielectric layer. There is then etched while employing a first plasma etch method the ion implanted portion of the blanket hard mask layer to form a patterned hard mask layer. Finally, there is then etched while employing a second plasma etch method employing the oxygen containing plasma the blanket second dielectric layer to form a patterned second dielectric layer having an aperture formed therethrough, where the aperture comprises a trench and at least a portion of the via.

公开(公告)号：US06255734B1

公开(公告)日：2001-07-03

申请号：US09670325

申请日：2000-09-27

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L2348

CPC分类号： H01L23/53238 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu3Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.

摘要翻译： 一种形成用于薄膜电子器件的铜导体的方法包括：在导体上形成层叠在衬底顶部以上的阻挡层堆叠，在阻挡层顶部的铜层和顶部的硬掩模层 的铜层。 在硬掩模层的顶部上形成掩模，并通过将层压蚀成形成铜层的掩模的侧面上的衬底到铜导体线中并且使铜导体线的侧壁露出而形成叠层。 生长铜锗化合物（Cu3Ge）化合物钝化层仅选择性地生长在铜导线的侧壁上。

公开(公告)号：US06221758B1

公开(公告)日：2001-04-24

申请号：US09225064

申请日：1999-01-04

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

公开(公告)号：US06207568B1

公开(公告)日：2001-03-27

申请号：US09200554

申请日：1998-11-27

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/76841 ,  H01L21/2855 ,  H01L21/28568 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias sputtering method. Finally there is then formed upon the titanium layer an aluminum containing conductor layer. By employing the ionized metal plasma bias sputtering method for forming the titanium layer, the aluminum containing conductor layer is formed with an enhanced (111) crystallographic orientation. The method is particularly useful for forming aluminum containing conductor layers with enhanced electromigration resistance, even under circumstances where there is formed interposed between a titanium layer and an aluminum containing conductor layer a titanium nitride layer.

摘要翻译： 一种形成含铝导体层的方法。 首先提供基板。 然后在衬底上形成采用电离金属等离子体偏置溅射方法的钛层。 最后，在钛层上形成含有铝的导体层。 通过采用用于形成钛层的电离金属等离子体偏压溅射法，形成具有增强（111）晶体取向的含铝导体层。 该方法对于形成具有增强的电迁移电阻的含铝导体层特别有用，即使在钛层和含铝导体层之间形成氮化钛层的情况下也是如此。

公开(公告)号：US06191025B1

公开(公告)日：2001-02-20

申请号：US09349847

申请日：1999-07-08

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited. Trenches are then etched in the fourth dielectric using the second dielectric, which has been maintained intact by the sacrificial third dielectric, as an etch stop. The trenches are then filled with a second barrier metal and second conductor metal. Excess second barrier metal and second conductor metal are then removed using chemical mechanical polishing to complete the damascene structure.

摘要翻译： 一种制造铜导体镶嵌结构的方法。 在其上形成有器件的硅衬底上形成第一，第二和第三电介质层。 第二电介质将随后作为蚀刻停止。 第三电介质是用于保护第二电介质的牺牲层。 然后在第一，第二和第三电介质的层中蚀刻接触孔。 然后沉积第一阻挡金属和第一导体金属，填充接触孔。 然后使用诸如化学机械抛光的方法将第一阻挡金属和第一导体金属去除到第三电介质层的原始顶表面和第二电介质的顶表面之间的水平。 牺牲的第三绝缘体在化学机械抛光期间保护第二电介质层。 然后沉积第四电介质层。 然后使用已被牺牲的第三电介质保持的第二电介质作为蚀刻停止层，在第四电介质中蚀刻沟槽。 然后用第二阻挡金属和第二导体金属填充沟槽。 然后使用化学机械抛光去除过量的第二阻挡金属和第二导体金属，以完成镶嵌结构。

公开(公告)号：US6130157A

公开(公告)日：2000-10-10

申请号：US356005

申请日：1999-07-16

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76879

摘要： A method to form copper interconnects with an improved encapsulation layer is achieved. A substrate layer is provided. Conductive traces are provided overlying the substrate layer. A first intermetal dielectric layer is deposited overlying the conductive traces. The first intermetal dielectric layer is etched through to the underlying conductive traces where the first intermetal dielectric layer is not protected by a photoresist mask to form interconnect trenches. A barrier layer is deposited overlying the first intermetal dielectric layer and exposed the conductive traces. A copper layer is deposited overlying the barrier layer and filling the interconnect trenches. The copper layer and the barrier layer are polished down to the top surface of the first intermetal dielectric layer to define copper interconnects. An encapsulation layer is formed overlying the copper interconnects wherein the encapsulation layer is not formed overlying the first intermetal interconnect layer and wherein the encapsulation layer is at least partially comprised of tungsten nitride. A second intermetal dielectric layer is deposited and the fabrication of the integrated circuit device is completed.

摘要翻译： 实现了与改进的封装层形成铜互连的方法。 提供基底层。 覆盖衬底层的导电迹线被提供。 第一金属间电介质层沉积在导电迹线上。 第一金属间电介质层被蚀刻到下面的导电迹线，其中第一金属间电介质层不被光致抗蚀剂掩模保护以形成互连沟槽。 沉积覆盖在第一金属间电介质层上并且暴露导电迹线的阻挡层。 沉积铜层沉积在阻挡层上并填充互连沟槽。 铜层和阻挡层被抛光到第一金属间电介质层的顶表面以限定铜互连。 形成覆盖铜互连的封装层，其中封装层没有形成在第一金属间互连层上，其中封装层至少部分地由氮化钨组成。 沉积第二金属间电介质层并完成集成电路器件的制造。

公开(公告)号：US6010962A

公开(公告)日：2000-01-04

申请号：US249262

申请日：1999-02-12

申请人： Chung-Shi Liu ,  Chung-Long Chang ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chung-Long Chang ,  Chen-Hua Yu

IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76879 ,  H01L21/32115

摘要： A method is disclosed for forming inlaid copper interconnects in an insulating layer without the normally expected dishing that occurs after chemical-mechanical polishing of the excess copper. This is accomplished by forming a conformal blanket barrier layer over a substrate including a composite groove/hole structure already formed in an insulating layer and then growing a copper seed layer over the barrier layer. A layer of photoresist is next deposited over the substrate filling the composite structure. The photoresist layer, seed layer and the barrier layer are then removed by chemical-mechanical polishing, leaving the seed layer and the barrier layer on the inside walls of the composite structure, however. Then the photoresist is removed from the composite structure, and replaced, in its place, with electroless plated copper, which forms a dome-like protrusion extending from the composite structure. When the substrate is subjected to chemical-mechanical polishing in order to remove the excess copper, the dome-like structure prevents the dishing of the copper metal. In a second embodiment, the seed layer and the barrier layer are chemical-mechanical polished without first depositing a photoresist layer. Copper metal is next selectively formed by electroless plating having a dome-like protrusion, which in turn is removed by chemical-mechanical polishing without the detrimental formation of dishing in the copper metal.

摘要翻译： 公开了一种用于在绝缘层中形成镶嵌铜互连的方法，而不会在多余的铜的化学机械抛光之后发生通常预期的凹陷。 这通过在包括已经形成在绝缘层中的复合凹槽/孔结构的衬底上形成共形覆盖层阻挡层，然后在阻挡层上生长铜籽晶层来实现。 接着在填充复合结构的基板上沉积一层光致抗蚀剂。 然后通过化学机械抛光除去光致抗蚀剂层，种子层和阻挡层，然而将种子层和阻挡层留在复合结构的内壁上。 然后将光致抗蚀剂从复合结构中去除，并在其位置上用化学镀铜替代，其形成从复合结构延伸的圆顶状突起。 当基板进行化学机械抛光以去除多余的铜时，圆顶状结构防止铜金属的凹陷。 在第二实施例中，晶种层和阻挡层在没有首先沉积光致抗蚀剂层的情况下进行化学机械抛光。 接下来通过具有圆顶状突起的化学镀选择性地形成铜金属，其通过化学机械抛光而被除去，而不会有害地形成铜金属中的凹陷。