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公开(公告)号：US11669669B2
公开(公告)日：2023-06-06
申请号：US16943827
申请日：2020-07-30
发明人： Chin-Shen Lin , Wan-Yu Lo , Shao-Huan Wang , Kuo-Nan Yang , Chung-Hsing Wang , Sheng-Hsiung Chen , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/392 , G06F30/347 , H01L21/78
CPC分类号： G06F30/392 , G06F30/347 , H01L21/78
摘要： A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.
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公开(公告)号：US20220384344A1
公开(公告)日：2022-12-01
申请号：US17332072
申请日：2021-05-27
发明人： Sheng-Hsiung Chen , Jerry Chang Jui Kao , Kuo-Nan Yang , Jack Liu
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , G06F30/392 , G06F30/394
摘要： An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.
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公开(公告)号：US11205032B2
公开(公告)日：2021-12-21
申请号：US16592200
申请日：2019-10-03
发明人： Chin-Shen Lin , Chung-Hsing Wang , Kuo-Nan Yang , Hiranmay Biswas
IPC分类号： G06F30/392 , G06F30/3308 , G06F30/337 , G06F30/398 , G06F119/06
摘要： A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.
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公开(公告)号：US10726174B2
公开(公告)日：2020-07-28
申请号：US15650131
申请日：2017-07-14
发明人： Chin-Shen Lin , Meng-Xiang Lee , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F30/367 , G06F30/30 , G01R31/28 , G06F30/333 , G06F119/12
摘要： A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.
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公开(公告)号：US09984192B2
公开(公告)日：2018-05-29
申请号：US15043858
申请日：2016-02-15
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
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公开(公告)号：US09509301B2
公开(公告)日：2016-11-29
申请号：US13931514
申请日：2013-06-28
发明人： Jerry Chang-Jui Kao , Chien-Ju Chao , Chou-Kun Lin , Chin-Shen Lin , King-Ho Tam , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： H02M3/156 , H03K17/296 , H03K17/284
CPC分类号： H03K17/296 , H03K17/284 , Y10T307/406
摘要： A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.
摘要翻译： 公开了一种包括多个电压控制电路的电路。 电压控制电路的每个电压控制电路包括驱动电路和开关电路。 驱动器电路被配置为接收具有一系列脉冲的控制信号。 开关电路被配置为在导通时产生驱动电压。 驱动器电路根据该脉冲串交替地接通和断开开关电路。
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公开(公告)号：US09317647B2
公开(公告)日：2016-04-19
申请号：US14231200
申请日：2014-03-31
发明人： Shyh-Horng Yang , Chung-Kai Lin , Chung-Hsing Wang , Kuo-Nan Yang , Shou-En Liu , Jhong-Sheng Wang , Tan-Li Chou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/80
摘要： A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.
摘要翻译： 一种设计电路的方法包括接收电路设计，并确定电路设计的至少后端（BEOL）元件的温度变化。 该方法还包括识别电路设计内的至少一个等温区域; 以及使用处理器确定所述至少一个等温区域内的至少一个前端（FEOL）装置的温度升高。 该方法还包括将至少一个BEOL元件的温度变化与至少一个FEOL装置的温度变化组合，以及将组合的温度变化与阈值进行比较。
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公开(公告)号：US09201107B2
公开(公告)日：2015-12-01
申请号：US14059332
申请日：2013-10-21
CPC分类号： G01R27/2605 , G01R27/2694 , G06F17/5063 , G06F2217/78
摘要： A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor.
摘要翻译： 利用米勒电容进行电池表征的方法包括通过考虑在第一级的输入到第一停止时间的第一电流转变来表征单元中的第一级的输入的输入电容。 在第一电流转换期间发生的第一停止时间表现出由稍后的第一输入电压转变和达到相应稳态电压的第一输出电压转换所引起的实质尾部。 第一输入电压转换与第一级的输入相关联。 第一输出电压转换与通过电容耦合到输入的第一级的输出相关联。
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公开(公告)号：US20150118812A1
公开(公告)日：2015-04-30
申请号：US14543991
申请日：2014-11-18
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： H01L29/66 , H01L21/8234
CPC分类号： H01L29/66545 , H01L21/823412 , H01L27/0207 , H01L27/0705 , H01L27/11807
摘要： An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
摘要翻译： 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。
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公开(公告)号：US12107048B2
公开(公告)日：2024-10-01
申请号：US18156086
申请日：2023-01-18
发明人： Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang , Meng-Xiang Lee , Hao-Tien Kan , Jhih-Hong Ye
IPC分类号： H01L23/528 , H01L23/522
CPC分类号： H01L23/5286 , H01L23/5226
摘要： Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
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