公开(公告)号：US12093625B2

公开(公告)日：2024-09-17

申请号：US17245130

申请日：2021-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Yu Lo ,  Kuo-Nan Yang ,  Chin-Shen Lin ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/392 ,  G06F111/10 ,  G06F111/20 ,  G06F119/08

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F2111/10 ,  G06F2111/20 ,  G06F2119/08

Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

公开(公告)号：US12019972B2

公开(公告)日：2024-06-25

申请号：US18302813

申请日：2023-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Nan Yang ,  Wan-Yu Lo ,  Chung-Hsing Wang ,  Hiranmay Biswas

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.

公开(公告)号：US12014982B2

公开(公告)日：2024-06-18

申请号：US17463203

申请日：2021-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Yu Lin ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang ,  Chih-Liang Chen ,  Lee-Chung Lu

IPC: G06F30/30 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L23/528 ,  H01L27/07 ,  H01L27/118 ,  H01L29/417 ,  H01L27/02

CPC classification number: H01L23/528 ,  G06F30/347 ,  G06F30/392 ,  G06F30/394 ,  H01L23/50 ,  H01L27/07 ,  H01L27/11807 ,  H01L29/41733 ,  H01L27/0207 ,  H01L2027/11879 ,  H01L2027/11881 ,  H01L2027/11887

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

公开(公告)号：US11929331B2

公开(公告)日：2024-03-12

申请号：US18067728

申请日：2022-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Wan-Yu Lo ,  Meng-Xiang Lee ,  Hao-Tien Kan ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/538 ,  H05K1/02

CPC classification number: H01L23/5386 ,  H05K1/0298

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

公开(公告)号：US11727183B2

公开(公告)日：2023-08-15

申请号：US17828911

申请日：2022-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

IPC: G06F30/392 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/394 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/52

CPC classification number: G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53271 ,  G06F30/394 ,  G06F30/3947 ,  G06F30/3953

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.

公开(公告)号：US11704469B2

公开(公告)日：2023-07-18

申请号：US17325787

申请日：2021-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： John Lin ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/39 ,  G06F30/398 ,  G03F1/82 ,  G03F1/70 ,  G03F1/36

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G03F1/82

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a first voltage supply having the first supply voltage.

公开(公告)号：US11532562B2

公开(公告)日：2022-12-20

申请号：US16911343

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Wan-Yu Lo ,  Meng-Xiang Lee ,  Hao-Tien Kan ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/538 ,  H05K1/02

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

公开(公告)号：US11239154B2

公开(公告)日：2022-02-01

申请号：US14600619

申请日：2015-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chien-Ju Chao ,  Fang-Yu Fan ,  Yi-Chuin Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/522 ,  H01L23/528 ,  G06F30/394

Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.

公开(公告)号：US11017146B2

公开(公告)日：2021-05-25

申请号：US16460439

申请日：2019-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： John Lin ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

IPC: G06F30/398 ,  G03F1/82 ,  G03F1/70 ,  G03F1/36

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.

公开(公告)号：US10943045B2

公开(公告)日：2021-03-09

申请号：US16222855

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

IPC: G06F17/50 ,  H01L23/52 ,  G06F30/392 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  G06F30/3947 ,  G06F30/3953

Abstract: A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i≥0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding adjacent ones of the third segments.