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公开(公告)号：US20180097611A1
公开(公告)日：2018-04-05
申请号：US15832836
申请日：2017-12-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne
CPC classification number: H04L7/027 , H03M9/00 , H04L1/0045 , H04L7/0008 , H04L7/0066 , H04L7/0079 , H04L7/0091 , H04L25/026 , H04L25/0272 , H04L25/14
Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.
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公开(公告)号：US09876630B2
公开(公告)日：2018-01-23
申请号：US14978381
申请日：2015-12-22
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: H04L7/027 , H03M9/00 , H04L1/0045 , H04L7/0008 , H04L7/0066 , H04L7/0079 , H04L7/0091 , H04L25/026 , H04L25/0272 , H04L25/14
Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.
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公开(公告)号：US09864398B2
公开(公告)日：2018-01-09
申请号：US14983776
申请日：2015-12-30
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: G06F1/04 , H04B1/04 , H04B1/16 , H04L25/4904
Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.
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公开(公告)号：US20170295045A1
公开(公告)日：2017-10-12
申请号：US15634668
申请日：2017-06-27
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: H04L25/4927 , H03M9/00 , H04L7/0008 , H04L7/0087 , H04L7/042
Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.
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公开(公告)号：US20170271736A1
公开(公告)日：2017-09-21
申请号：US15614969
申请日：2017-06-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Floyd Payne , Gerd Schuppener , Juan Alejandro Herbsommer
CPC classification number: H01P3/16 , H01P11/006
Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.
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Patent Agency Ranking
公开(公告)号：US09722824B2
公开(公告)日：2017-08-01
申请号：US14985254
申请日：2015-12-30
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: H04L25/4927 , H03M9/00 , H04L7/0008 , H04L7/0087 , H04L7/042
Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.
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公开(公告)号：US20170195148A1
公开(公告)日：2017-07-06
申请号：US14985254
申请日：2015-12-30
Applicant: Texas Instruments Incorporated
Inventor： Robert Floyd Payne
CPC classification number: H04L25/4927 , H03M9/00 , H04L7/0008 , H04L7/0087 , H04L7/042
Abstract: A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.
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公开(公告)号：US20170093009A1
公开(公告)日：2017-03-30
申请号：US14865552
申请日：2015-09-25
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Robert Floyd Payne
CPC classification number: H01P5/087 , H01P1/042 , H01P3/026 , H01P3/16 , H01Q1/2283 , H01Q13/085 , H01R24/64
Abstract: A dielectric waveguide socket is provided with a dielectric waveguide (DWG) stub having a dielectric core member surrounded by dielectric cladding, the DWG stub having an interface end and an opposite mating end. A socket body is coupled to the DWG stub, such that a mounting surface of the socket body is configured to mount the socket body on a substrate such that the core member of DWG stub forms an angle of inclination with the substrate. The socket body is configured to couple with the end of a DWG cable, such that the end of the DWG cable is held in alignment with the mating end of the DWG stub.
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59.发明授权Interface between an integrated circuit and a dielectric waveguide using a carrier substrate with a dipole antenna and a reflector 有权使用具有偶极天线和反射器的载体衬底的集成电路和介质波导之间的接口公开(公告)号：US09300025B2
公开(公告)日：2016-03-29
申请号：US13854958
申请日：2013-04-02
Applicant: Texas Instruments Incorporated
Inventor： Juan Alejandro Herbsommer , Gerd Schuppener , Robert Floyd Payne
IPC: H01P5/107 , H01P3/16 , H01P5/08 , G02B6/44 , H01P11/00 , H01P5/00 , H01Q1/50 , H01Q19/10 , H04B1/40 , H01Q19/30 , H01P3/12
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency (RF) amplifier configured to produce an RF signal or an RF receiver configured to receive an RF signal is formed on the top surface of the substrate. A through-substrate via is coupled to an output of the RF amplifier. A metalized antenna formed on the bottom surface of the substrate is coupled to the through-substrate via. The metalized antenna is configured to launch an electromagnet wave representative of the RF signal into a dielectric waveguide (DWG) when the DWG is coupled to the bottom side of the substrate.
Abstract translation: 一种系统包括具有顶表面和底表面的基底的集成电路。 半导体电路包括被配置为产生RF信号的射频（RF）放大器或被配置为接收RF信号的RF接收器，该RF接收器被形成在衬底的顶表面上。 穿通基板通孔耦合到RF放大器的输出端。 形成在基板的底表面上的金属化天线与穿通基板通孔相连。 当DWG耦合到衬底的底侧时，金属化天线被配置为将代表RF信号的电磁波发射到电介质波导（DWG）中。
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60.发明授权Interface between an integrated circuit and a dielectric waveguide using a dipole antenna, a reflector and a plurality of director elements 有权使用偶极子天线，反射器和多个导向器元件的集成电路和电介质波导之间的接口公开(公告)号：US09300024B2
公开(公告)日：2016-03-29
申请号：US13854957
申请日：2013-04-02
Applicant: Texas Instruments Incorporated
Inventor： Gerd Schuppener , Juan Alejandro Herbsommer , Robert Floyd Payne
IPC: H01P5/107 , H01P3/16 , H01P5/08 , G02B6/44 , H01P11/00 , H01P5/00 , H01Q1/50 , H01Q19/10 , H04B1/40 , H01Q19/30 , H01P3/12
CPC classification number: H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
Abstract: A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an interface surface configured for interfacing to the mating end of the DWG. A conductive layer is etched to form a dipole antenna disposed adjacent the interface surface. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. A set of director elements is embedded in the mating end of the DWG. Specific spacing is maintained between the dipole antenna and the set of director elements.
Abstract translation: 一种系统包括耦合到电介质波导（DWG）的配合端的电子装置。 电子设备具有多层基板，该多层基板具有被配置为与DWG的配合端对接的界面。 蚀刻导电层以形成邻近界面表面设置的偶极天线。 反射器结构形成在与界面表面相对的偶极子天线附近的衬底中。 一组指导元素嵌入在DWG的配对端。 在偶极天线和导向器元件组之间保持特定的间隔。
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