公开(公告)号：US20150171211A1

公开(公告)日：2015-06-18

申请号：US14563028

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Yongxi ZHANG ,  Sameer PENDHARKAR ,  Seetharaman SRIDHAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.

Abstract translation: 一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。 具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。 深沟槽隔离横向围绕隔离设备。 在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

公开(公告)号：US20150097225A1

公开(公告)日：2015-04-09

申请号：US14044909

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract translation: 半导体器件具有深沟槽结构的垂直漏极扩展MOS晶体管，以限定垂直漂移区域和至少一个垂直漏极接触区域，其通过深沟槽结构的至少一个实例与垂直漂移区域分离。 将掺杂剂注入到垂直漏极接触区域中，并且半导体器件被退火，使得注入的掺杂剂在深沟槽结构的底部附近扩散。 垂直漏极接触区域在中间深沟槽结构的底部处与邻近的垂直漂移区域电接触。 至少一个栅极，主体区域和源极区域形成在半导体器件的衬底的顶表面处或附近的漂移区域上方。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。