公开(公告)号：US10956647B2

公开(公告)日：2021-03-23

申请号：US16214243

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

公开(公告)号：US10678990B2

公开(公告)日：2020-06-09

申请号：US16205441

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: G06F17/50 ,  G06F30/394 ,  H01L23/528 ,  G06F30/392 ,  G06F30/398 ,  G06F30/347 ,  G06F30/373 ,  H01L27/02 ,  G06F30/396 ,  G06F119/10 ,  G06F117/12

Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

公开(公告)号：US10515175B2

公开(公告)日：2019-12-24

申请号：US15723308

申请日：2017-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F17/50

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

公开(公告)号：US09384307B2

公开(公告)日：2016-07-05

申请号：US13970636

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5072 ,  G06F2217/78

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

公开(公告)号：US09026953B2

公开(公告)日：2015-05-05

申请号：US14064229

申请日：2013-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Yu Chen ,  Chin-Hsiung Hsu ,  Wen-Hao Chen ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract translation: 一种方法包括（a）提供集成电路（IC）布局，其包括通过多图案化表示要形成在IC的单层上或其中的多个电路图案的数据; （b）将所述多个电路图案分成两组或更多组; （c）将每个组内的电路图案分配给相应的掩模以提供掩模分配数据，以在IC上或其单层中形成每组电路图案; （d）压缩掩模分配数据; 以及（e）将压缩的掩模分配数据存储到非暂时的机器可读存储介质，以供配置用于从压缩数据重建掩模分配数据的电子设计自动化工具使用。

公开(公告)号：US08732641B1

公开(公告)日：2014-05-20

申请号：US13677380

申请日：2012-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hung Yuh ,  Hsin-Yun Lin ,  Cheng-I Huang ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5036 ,  G06F17/5081

Abstract: The present disclosure relates to a method and apparatus for accurate RC extraction. A pattern database is configured to store layout patterns and their associated 3D extraction parameters. A pattern-matching tool is configured to partition a design into a plurality of patterns, and to search the pattern database for a respective pattern and associated 3D extraction parameters. If the respective pattern is already stored in the pattern database, then the associated 3D extraction parameters stored in the database are assigned to the respective pattern without the need to extract the respective pattern. If the respective pattern is not stored in the pattern database, then the extraction tool extracts the pattern and stores its associated 3D extraction parameters in the pattern database for future use. In this manner a respective pattern is extracted only once for a given design or plurality of designs. Moreover, the extraction result may be applied multiple times for a given design simultaneously, speeding up computation time. The extraction result may also be applied to a plurality of designs simultaneously.

Abstract translation: 本公开涉及一种用于精确RC提取的方法和装置。 模式数据库被配置为存储布局模式及其相关的3D提取参数。 模式匹配工具被配置为将设计分割成多个模式，并且搜索模式数据库中的相应模式和相关联的3D提取参数。 如果相应的图案已经存储在图案数据库中，则存储在数据库中的相关3D提取参数被分配给相应的图案，而不需要提取相应的图案。 如果相应的图案不存储在图案数据库中，则提取工具提取图案并将其相关联的3D提取参数存储在图案数据库中以供将来使用。 以这种方式，对于给定的设计或多个设计，相应的图案仅被提取一次。 此外，提取结果可以同时应用于给定设计的多次，从而加快了计算时间。 提取结果也可以同时应用于多个设计。