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    DIAGONAL TORUS NETWORK
    2.
    发明申请
    DIAGONAL TORUS NETWORK 有权

    公开(公告)号：US20230066045A1

    公开(公告)日：2023-03-02

    申请号：US17461225

    申请日：2021-08-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Yung-Chen Chien ,  Tzu-Ying Lin ,  Wei-Hsiang Ma ,  Chung-Hsing Wang

    IPC: G06F15/173 ,  G06F15/17

    Abstract: A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

    PROMOTING EFFICIENT CELL USAGE TO BOOST QOR IN AUTOMATED DESIGN
    4.
    发明申请
    PROMOTING EFFICIENT CELL USAGE TO BOOST QOR IN AUTOMATED DESIGN 有权
    促进高效电池在自动化设计中的应用

    公开(公告)号：US20150128101A1

    公开(公告)日：2015-05-07

    申请号：US14072060

    申请日：2013-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu Chen ,  Ya Chen Wang ,  Tan-Li Chou

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077

    Abstract: A method of designing integrated circuits includes forming a restricted cell library from a first cell library by selecting only those cells in the first cell library that are most efficient according to predetermined efficiency criteria and executing an integrated circuit design operation in an electronic design automation program while directing the electronic design automation program to make cell selections exclusively from the restricted cell library. The integrated circuit design operation is one that can be directed to make cell selections from any of the cells in the first cell library without changing its essential purpose. The method improves QoR for the resulting circuit design.

    Abstract translation: 设计集成电路的方法包括：通过仅根据预定效率标准选择最有效的第一单元库中的那些单元，并且在电子设计自动化程序中执行集成电路设计操作，从第一单元库形成受限单元库， 指导电子设计自动化程序，使细胞从限制性细胞库专门选择。 集成电路设计操作是可以针对第一单元库中的任何单元进行单元格选择而不改变其基本目的的操作。 该方法提高了所得到的电路设计的QoR。

    Compression method and system for use with multi-patterning
    5.
    发明授权
    Compression method and system for use with multi-patterning 有权
    压缩方法和系统用于多图案化

    公开(公告)号：US09026953B2

    公开(公告)日：2015-05-05

    申请号：US14064229

    申请日：2013-10-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu Chen ,  Chin-Hsiung Hsu ,  Wen-Hao Chen ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G03F1/70 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

    Abstract translation: 一种方法包括（a）提供集成电路（IC）布局，其包括通过多图案化表示要形成在IC的单层上或其中的多个电路图案的数据; （b）将所述多个电路图案分成两组或更多组; （c）将每个组内的电路图案分配给相应的掩模以提供掩模分配数据，以在IC上或其单层中形成每组电路图案; （d）压缩掩模分配数据; 以及（e）将压缩的掩模分配数据存储到非暂时的机器可读存储介质，以供配置用于从压缩数据重建掩模分配数据的电子设计自动化工具使用。

    Cell layout of semiconductor device
    6.
    发明授权
    Cell layout of semiconductor device 有权

    公开(公告)号：US12039251B2

    公开(公告)日：2024-07-16

    申请号：US18156912

    申请日：2023-01-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Lin Chuang ,  Huang-Yu Chen ,  Yun-Han Lee

    IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F30/396

    CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F30/396

    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

    Promoting efficient cell usage to boost QoR in automated design
    9.
    发明授权
    Promoting efficient cell usage to boost QoR in automated design 有权
    促进有效的细胞使用，以提高自动化设计中的QoR

    公开(公告)号：US09355202B2

    公开(公告)日：2016-05-31

    申请号：US14072060

    申请日：2013-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu Chen ,  Ya Chen Wang ,  Tan-Li Chou

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077

    Abstract: A method of designing integrated circuits includes forming a restricted cell library from a first cell library by selecting only those cells in the first cell library that are most efficient according to predetermined efficiency criteria and executing an integrated circuit design operation in an electronic design automation program while directing the electronic design automation program to make cell selections exclusively from the restricted cell library. The integrated circuit design operation is one that can be directed to make cell selections from any of the cells in the first cell library without changing its essential purpose. The method improves QoR for the resulting circuit design.

    Abstract translation: 设计集成电路的方法包括：通过仅根据预定效率标准选择最有效的第一单元库中的那些单元，并且在电子设计自动化程序中执行集成电路设计操作，从第一单元库形成受限单元库， 指导电子设计自动化程序，使细胞从限制性细胞库专门选择。 集成电路设计操作是可以针对第一单元库中的任何单元进行单元格选择而不改变其基本目的的操作。 该方法提高了所得到的电路设计的QoR。

    Layout method and system for multi-patterning integrated circuits
    10.
    发明授权
    Layout method and system for multi-patterning integrated circuits 有权
    多图案集成电路的布局方法和系统

    公开(公告)号：US09262577B2

    公开(公告)日：2016-02-16

    申请号：US14267013

    申请日：2014-05-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu Chen ,  Tsong-Hua Ou ,  Ken-Hsien Hsieh ,  Chin-Hsiung Hsu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/12

    Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

    Abstract translation: 一种方法将作为独立节点的任何节点表示在不包括在布局的任何其它奇数循环中的IC层的区域的布局的任何奇数循环中的电路图案。 该层将具有使用至少三个光掩模进行图案化的多个电路图案。 该方法将安全独立节点识别为距离布局的另一个奇数循环中任何其他独立节点不超过阈值距离的任何独立节点。 布局被修改，如果布局中的电路图案包括没有任何安全独立节点的任何奇数循环，使得在修改之后，每个奇数循环至少有一个安全独立节点。

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