公开(公告)号：US11133044B2

公开(公告)日：2021-09-28

申请号：US15995578

申请日：2018-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Chung-Te Lin ,  Min Cao ,  Randy Osborne

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.

公开(公告)号：US20200303456A1

公开(公告)日：2020-09-24

申请号：US16896369

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

公开(公告)号：US20200105830A1

公开(公告)日：2020-04-02

申请号：US16416529

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

公开(公告)号：US10535520B2

公开(公告)日：2020-01-14

申请号：US15684282

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Li-Te Lin ,  Ru-Gun Liu ,  Min Cao

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.

公开(公告)号：US20190006391A1

公开(公告)日：2019-01-03

申请号：US15800390

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.