公开(公告)号：US20220359331A1

公开(公告)日：2022-11-10

申请号：US17869003

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region.

公开(公告)号：US11488882B2

公开(公告)日：2022-11-01

申请号：US16989047

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/60

Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

公开(公告)号：US11482508B2

公开(公告)日：2022-10-25

申请号：US16934041

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/49 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

Abstract: A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes conductive pads disposed at the active surface. A first solder-containing alloy layer is formed on the rear surface of the chip. A second solder-containing alloy layer is formed on a surface and at a location where the chip is to be attached. The chip is mounted to the surface and the first solder-containing alloy layer is aligned with the second solder-containing alloy layer. A reflow step is performed on the first and second solder-containing alloy layers to form a joint alloy layer between the chip and the surface.

公开(公告)号：US11456287B2

公开(公告)日：2022-09-27

申请号：US16846400

申请日：2020-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Wen-Hsin Wei ,  Chih-Chien Pan

IPC: H01L23/053 ,  H01L23/10 ,  H01L25/16 ,  H01L23/16 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

公开(公告)号：US11417580B2

公开(公告)日：2022-08-16

申请号：US17012299

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US11270976B2

公开(公告)日：2022-03-08

申请号：US16454098

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Hang Liao ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsulant. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

公开(公告)号：US11094635B2

公开(公告)日：2021-08-17

申请号：US16548202

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00

Abstract: A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The package structure also includes a molding compound layer surrounding the interposer, and a second redistribution structure over the interposer. The molding compound layer is between the first redistribution structure and the second redistribution structure. The package structure further includes a first semiconductor die and a second semiconductor die over the second redistribution structure.

公开(公告)号：US11081369B2

公开(公告)日：2021-08-03

申请号：US16283851

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US11062968B2

公开(公告)日：2021-07-13

申请号：US16548165

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chih-Chien Pan ,  Li-Hui Cheng ,  Chin-Fu Kao ,  Szu-Wei Lu

IPC: H01L23/18 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes an interposer, a first semiconductor die and a second semiconductor die over the interposer. The method for forming a package structure also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component. The method for forming a package structure further includes forming an underfill layer between the dam structure and the package component, and removing the dam structure after the underfill layer is formed.

公开(公告)号：US11056364B2

公开(公告)日：2021-07-06

申请号：US16886800

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L21/67 ,  H01L23/00 ,  H01L21/683 ,  H01L21/687 ,  H01L21/56

Abstract: A method for thinning a substrate is provided. The method includes at least the following steps. A substrate is disposed on a carrying surface of a chuck, where a first liquid supply unit surrounds the chuck to form a frame of the chuck, and an outlet of the first liquid supply unit is disposed aside the carrying surface of the chuck. A first liquid flows from a bottom of the frame to the outlet and discharges to fill a gap between the substrate and the carrying surface of the chuck. The substrate is thinned during the gap is filled.