公开(公告)号：US08755296B2

公开(公告)日：2014-06-17

申请号：US13308635

申请日：2011-12-01

申请人： Masayuki Miyazaki ,  Kenichi Mizugaki ,  Masaru Kokubo ,  Hideyuki Nagaishi ,  Nobuhisa Kobayashi

发明人： Masayuki Miyazaki ,  Kenichi Mizugaki ,  Masaru Kokubo ,  Hideyuki Nagaishi ,  Nobuhisa Kobayashi

IPC分类号： H04L12/26

CPC分类号： H04W28/06 ,  H04L1/0002 ,  H04L1/0014 ,  H04L43/00 ,  H04L67/12 ,  H04L69/04 ,  H04L2001/0097 ,  H04W4/38 ,  H04W24/10 ,  H04W84/18 ,  Y02D70/00

摘要： A wireless communication device includes a sensor processing unit that generates sensor data including a measurement result acquired by a sensor; a communication measurement unit that generates communication quality data including a communication state for transmitting a packet; a compression determination unit that determines compression rates of first sensor data and first communication quality data according to the contents of the first sensor data including the transmitted sensor data and the generated sensor data or the contents of the first communication quality data including the transmitted sensor data and the generated communication quality data; a compression unit that compresses the first sensor data and the first communication quality data according to the determined compression rates; and a wireless communication unit that transmits a packet including the compressed first sensor data and the compressed first communication quality data to another wireless communication device or the access point.

摘要翻译： 无线通信装置包括传感器处理单元，其生成包括由传感器获取的测量结果的传感器数据; 通信测量单元，其生成包括用于发送分组的通信状态的通信质量数据; 压缩确定单元，其根据包括所发送的传感器数据和所生成的传感器数据的第一传感器数据的内容或包括所发送的传感器数据的第一通信质量数据的内容来确定第一传感器数据和第一通信质量数据的压缩率 和生成的通信质量数据; 压缩单元，其根据确定的压缩率压缩第一传感器数据和第一通信质量数据; 以及无线通信单元，其将包括压缩的第一传感器数据和压缩的第一通信质量数据的分组发送到另一无线通信设备或接入点。

公开(公告)号：US07808397B2

公开(公告)日：2010-10-05

申请号：US11822272

申请日：2007-07-03

申请人： Hiroshi Arita ,  Masaru Kokubo ,  Kenichi Mizugaki

发明人： Hiroshi Arita ,  Masaru Kokubo ,  Kenichi Mizugaki

IPC分类号： G08B23/00

CPC分类号： G08B25/10

摘要： A sensor transmits and receives wireless signals at intervals. A sensor unit, a processor 130, a wireless transmitter circuit, and a wireless receiver circuit are activated in sequence only for a fixed time when the electric power generated by a generator circuit and charged in a capacitor reaches a preset level. Sensing information detected by the sensor unit is processed by the processor circuit and, information on the number of receivable bytes is added to the processing results in the wireless receiver circuit. This added information is sent as sensor information to the wireless host from the wireless transmitting circuit, and the wireless receiver circuit that activated after the wireless transmitter circuit was activated, receives a control information signal from the wireless host. This received information is processed in the processor circuit.

摘要翻译： 传感器间隔地发送和接收无线信号。 传感器单元，处理器130，无线发射器电路和无线接收器电路仅在发电机产生的电力并在电容器中充电的电力达到预设电平的固定时间内被依次激活。 由传感器单元检测到的感测信息由处理器电路处理，并且关于可接收字节数的信息被添加到无线接收器电路中的处理结果。 该添加的信息作为传感器信息从无线发送电路发送到无线主机，并且在无线发射机电路被激活之后激活的无线接收机电路从无线主机接收控制信息信号。 该接收到的信息在处理器电路中被处理。

公开(公告)号：US07737792B2

公开(公告)日：2010-06-15

申请号：US12362486

申请日：2009-01-29

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/08

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US20090153204A1

公开(公告)日：2009-06-18

申请号：US12362486

申请日：2009-01-29

申请人： Takashi Kawamoto ,  Masaru Kokubo

发明人： Takashi Kawamoto ,  Masaru Kokubo

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/1976 ,  H03L2207/06

摘要： To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal. Also, the voltage controlled oscillator is capable of changing the frequency sensitivity of the output signal that is outputted with respect to the control voltage according to the trimming signal, and the upper limit frequency of the output signal according to the limit signal.

摘要翻译： 提供能够执行不依赖于工艺变化和环境变化的满足期望特性的自动调整的锁相环电路。 锁相环电路具有相位频率比较器，电荷泵，环路滤波器，分频器，选择器和压控振荡器。 分频器输入输出信号和参考信号，分频输出信号，并输出反馈信号，并从输出信号输出选择信号，微调信号和限幅信号。 压控振荡器输入控制电压，基极电压，微调信号和极限信号，根据控制电压改变输出信号频率，限制输出信号的上限频率。 此外，压控振荡器能够根据微调信号和根据限制信号的输出信号的上限频率来改变与控制电压相关的输出信号的频率灵敏度。

公开(公告)号：US07477676B2

公开(公告)日：2009-01-13

申请号：US10863507

申请日：2004-06-09

申请人： Masaru Kokubo ,  Yoshiyuki Shibahara

发明人： Masaru Kokubo ,  Yoshiyuki Shibahara

IPC分类号： H04B1/00

CPC分类号： G06F1/04 ,  G06F1/03 ,  H03L7/197 ,  H03L2207/06 ,  H04B15/04 ,  H04B2215/067

摘要： The present invention provides a spread spectrum clock generator that is capable of preventing phase jumps and jitters and suppressing the occurrence of Electro Magnetic Interference components and that can easily be applied to large scale integrated circuits. The spread spectrum clock generator can be configured with a filter, quantizer, fractional divider, and other elements. Also, this clock generator circuitry can be configured by combination of a delta-sigma ΔΣ quantizer and factional divider so that sine wave modulation and random number modulation can be realized. Thereby, control with digital values can be performed. This clock generator prevents precipitous phase variations in the output high frequency clock and makes fine phase control possible. Consequently, EMI reduction by 20-30 dB can be expected.

摘要翻译： 本发明提供一种扩频时钟发生器，其能够防止相位跳跃和抖动并抑制电磁干扰部件的发生，并且可以容易地应用于大规模集成电路。 扩频时钟发生器可以配置有滤波器，量化器，分数分频器和其他元件。 此外，该时钟发生器电路可以通过Δ-ΣΔΔSigma量化器和派系分频器的组合来配置，从而可以实现正弦波调制和随机数调制。 因此，可以执行具有数字值的控制。 该时钟发生器可以防止输出高频时钟中的陡峭相位变化，从而实现良好的相位控制。 因此，可以预期EMI降低20-30dB。

公开(公告)号：US20060261873A1

公开(公告)日：2006-11-23

申请号：US11403968

申请日：2006-04-14

申请人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

发明人： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC分类号： H03K12/00

CPC分类号： H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

摘要： A logical level converter generates an output signal by which succeeding logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

摘要翻译： 逻辑电平转换器产生输出信号，即使存在阈值波动因子，后续逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US20060197618A1

公开(公告)日：2006-09-07

申请号：US11334573

申请日：2006-01-19

申请人： Takayasu Norimatsu ,  Ryosuke Fujiwara ,  Masaru Kokubo ,  Akira Maeki

发明人： Takayasu Norimatsu ,  Ryosuke Fujiwara ,  Masaru Kokubo ,  Akira Maeki

IPC分类号： H03B29/00

CPC分类号： H04B1/7174 ,  H04L25/03834

摘要： The object is simplification of a configuration in a pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal. A pulse generator comprises: a clock generator (CLK) for giving clock of a predetermined period; a delay circuit (DLY) equipped with a function of controlling a delay time and for delaying the clock; a square-wave pulse generation circuit (SWPG), by receiving information being spread by a spread code, modulates phases of square wave pulses that have a pulse width corresponding to a differential delay for one stage of the delay circuit by comparing the signals outputted from the delay circuit and having different delay times, and outputs the square wave pulses; and an amplitude control unit (AMPC) that outputs an impulse sequence having the pulse width of the square wave in a predetermined amplitude by receiving a square wave pulse sequence outputted from the square-wave pulse generation circuit at different timings, and combines the impulses; and outputs pulses that have a predetermined envelope form.

摘要翻译： 目的是简化用于UWB传输的脉冲发生器中的配置，降低功耗，并且通过不使用LO信号来抑制LO泄漏。 脉冲发生器包括：用于给定预定周期的时钟的时钟发生器（CLK）; 具有控制延迟时间和延迟时钟的功能的延迟电路（DLY）; 方波脉冲发生电路（SWPG）通过接收由扩展码进行扩展的信息，通过比较输出的信号来调制具有对应于延迟电路的一级的差分延迟的脉冲宽度的方波脉冲的相位 延迟电路并具有不同的延迟时间，并输出方波脉冲; 以及振幅控制单元（AMPC），通过在不同的定时接收从方波脉冲发生电路输出的方波脉冲序列，输出具有预定振幅的方波脉冲宽度的脉冲序列，并组合脉冲; 并输出具有预定包络形式的脉冲。

公开(公告)号：US20060087909A1

公开(公告)日：2006-04-27

申请号：US11298514

申请日：2005-12-12

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C8/00

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

公开(公告)号：US20060084402A1

公开(公告)日：2006-04-20

申请号：US11251922

申请日：2005-10-18

申请人： Takashi Oshima ,  Masaru Kokubo

发明人： Takashi Oshima ,  Masaru Kokubo

IPC分类号： H04B1/06 ,  H04L27/08

CPC分类号： H04B1/1027

摘要： A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.

公开(公告)号：US06819626B2

公开(公告)日：2004-11-16

申请号：US10614242

申请日：2003-07-08

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C1100

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.