公开(公告)号：US20110080709A1

公开(公告)日：2011-04-07

申请号：US12652038

申请日：2010-01-05

Applicant: Tony Lin

Inventor： Tony Lin

IPC: H05K7/20

CPC classification number: H05K7/20972

Abstract: A digital signage player is provided. The digital signage player includes a body having a main board and a hard disk, an outer frame in which the body is framed, and a heat dissipation unit disposed in the body. The digital signage player of the present invention can be conveniently fixed to a wall surface nearby the digital signage by fixing a fixing mechanism of the outer frame with screw bolts or rivets to the wall surface. Further, the corrugation shaped heat dissipation fins are also configured to prevent dusts or dirts from entering the body and contaminating the main board.

Abstract translation: 提供数字标牌播放器。 数字标牌播放器包括具有主板和硬盘的主体，主体被框架的外框架和布置在主体中的散热单元。 通过将外框架的固定机构用螺栓或铆钉固定到墙壁表面上，本发明的数字标牌玩家可以方便地固定在数字标牌附近的墙壁表面上。 此外，波纹状散热片也被构造成防止灰尘或污物进入身体并污染主板。

公开(公告)号：USD630392S1

公开(公告)日：2011-01-04

申请号：US29352579

申请日：2009-12-22

Applicant: Tony Lin

Designer： Tony Lin

公开(公告)号：USD590284S1

公开(公告)日：2009-04-14

申请号：US29319426

申请日：2008-06-09

Applicant: James M. Critelli ,  Peter Lin ,  Tony Lin

Designer： James M. Critelli ,  Peter Lin ,  Tony Lin

公开(公告)号：US20060240666A1

公开(公告)日：2006-10-26

申请号：US10907891

申请日：2005-04-20

Applicant: Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Chien-Chung Huang ,  Po-Chao Tsou ,  Kirk Hsu ,  Tony Lin ,  Le-Tien Jung

Inventor： Chao-Ching Hsieh ,  Yi-Yiing Chiang ,  Chien-Chung Huang ,  Po-Chao Tsou ,  Kirk Hsu ,  Tony Lin ,  Le-Tien Jung

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/76889

Abstract: A method of forming silicide is described. A layer of refractory metal is deposited on a substrate, and then a first annealing process is performed to form silicide, followed by removal of unreacted metal. Next, a species implanting process is carried out to implant species of neutral atoms into the silicide to break up lattice structure of the silicide, so that the problem of junction leakage induced by spiking and piping diffusion under high temperature during a subsequent second annealing process is avoided.

Abstract translation: 描述了形成硅化物的方法。 将难熔金属层沉积在基材上，然后进行第一退火工艺以形成硅化物，随后除去未反应的金属。 接下来，进行物种植入工艺以将中性原子的种类植入到硅化物中以破坏硅化物的晶格结构，从而在随后的第二退火过程中由高温引起的尖峰和管道扩散引起的结漏电的问题是 避免。

公开(公告)号：US20050269195A1

公开(公告)日：2005-12-08

申请号：US11103918

申请日：2005-04-12

Applicant: Joseph Brandon ,  Tony Lin

Inventor： Joseph Brandon ,  Tony Lin

IPC: H01H71/04 ,  H01H71/12 ,  H01H71/24 ,  H01H71/52 ,  H01H71/74 ,  H01H83/22 ,  H01H5/00

CPC classification number: H01H71/524 ,  H01H71/04 ,  H01H71/123 ,  H01H71/2472 ,  H01H71/7409 ,  H01H83/226 ,  H01H2009/305 ,  H01H2071/042 ,  H01H2071/124

Abstract: A microprocessor-based circuit breaker includes a chip that defines the current rating or ground fault current for the breaker. Thus, the maximum current rating and/or ground fault current can be set after manufacture using the chip that is electrically connected to the microprocessor. The breaker includes mechanical components that trip to disconnect the load terminal from the line input. The mechanical components include a floating breaker arm, trigger and tripper lever that cooperate to control the tripping of the breaker. A spring between the breaker arm and trigger, together with cam surfaces defined in the breaker switch cooperate to form a floating linkage to control the position of the breaker arm during on/off activation and current fault conditions. The circuit breaker also includes multiple indicia to provide a visual indication of the type of fault condition sensed by the breaker.

Abstract translation: 基于微处理器的断路器包括限定断路器的额定电流或接地故障电流的芯片。 因此，可以在使用与微处理器电连接的芯片制造后，设定最大额定电流和/或接地故障电流。 断路器包括机械部件，其跳闸以将负载端子与线路输入断开。 机械部件包括一个浮动断路器臂，触发器和跳闸杆，用于控制断路器的跳闸。 断路器臂和触发器之间的弹簧以及限定在断路器开关中的凸轮表面协作以形成浮动联动装置，以在开/关激活和当前故障条件期间控制断路器臂的位置。 断路器还包括多个标记以提供由断路器感测到的故障状况的类型的可视指示。

公开(公告)号：US06316303B1

公开(公告)日：2001-11-13

申请号：US09504563

申请日：2000-02-15

Applicant: Tony Lin ,  Chien-Chao Huang ,  Ming-Yin Hao

Inventor： Tony Lin ,  Chien-Chao Huang ,  Ming-Yin Hao

IPC: H01L218238

CPC classification number: H01L29/66492 ,  H01L21/28052 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628

Abstract: A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.

Abstract translation: 一种制造具有SEG Si的MOS晶体管的方法。 在形成栅极和间隔物之后，在形成源极/漏极区之前，在衬底上沉积选择性外延生长（SEG）Si。 然后在形成SEG Si之后，将间隔物移除以在被间隔物覆盖的暴露的基底中形成超浅结。

公开(公告)号：USD449860S1

公开(公告)日：2001-10-30

申请号：US29137546

申请日：2001-02-26

Applicant: Tony Lin

Designer： Tony Lin

公开(公告)号：US06297112B1

公开(公告)日：2001-10-02

申请号：US09497668

申请日：2000-02-04

Applicant: Tony Lin ,  Tung-Po Chen ,  Ming-Yin Hao

Inventor： Tony Lin ,  Tung-Po Chen ,  Ming-Yin Hao

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/6656 ,  Y10S438/976

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor. The portion of the first ion implantation layer that is not covered by the second ion implantation layer is used as a lightly doped drain (LDD). The protection layer is used to protect the surface of the silicon substrate from being etched during the RCA cleaning process so as to prevent an increase of the electrical resistance of the LDD.

Abstract translation: 本发明提供一种在半导体晶片上形成PMOS晶体管或NMOS晶体管的方法。 半导体晶片包括硅衬底和位于硅衬底的预定区域上的栅极。 首先，在半导体晶片上形成由氮化硅制成的均匀厚度的保护层，以覆盖栅极的表面。 然后，进行第一离子注入工艺以在栅极周围的硅衬底上形成具有第一预定厚度的第一离子注入层。 然后，执行RCA清洁处理以去除半导体晶片上的杂质。 接下来，在栅极周围形成间隔物。 最后，执行第二离子注入工艺以在栅极周围的硅衬底上形成具有第二预定厚度的第二离子注入层。 第二离子注入层用作MOS晶体管的源极或漏极（S / D）。 未被第二离子注入层覆盖的第一离子注入层的部分用作轻掺杂漏极（LDD）。 保护层用于在RCA清洁过程中保护硅衬底的表面不被蚀刻，以防止LDD的电阻增加。

公开(公告)号：US06294432B1

公开(公告)日：2001-09-25

申请号：US09467632

申请日：1999-12-20

Applicant: Tony Lin ,  Jih-Wen Chou

Inventor： Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode formed thereon and a halo implant region formed therein. Then, a dielectric layer is deposited on the substrate and the gate electrode. Next, the semiconductor structure is annealed, and the dielectric layer is anisotropically etched to form an offset spacer.

Abstract translation: 公开了一种通过使用与偏移间隔物工艺组合的超晕晕植入物形成半导体结构的方法。 本发明包括提供其上形成有栅电极的基板和形成在其中的光晕注入区域。 然后，在基板和栅电极上沉积电介质层。 接下来，对半导体结构进行退火，并且电介质层被各向异性地蚀刻以形成偏移间隔物。

公开(公告)号：US06274448B1

公开(公告)日：2001-08-14

申请号：US09208621

申请日：1998-12-08

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Jih-Wen Chou

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513

Abstract: A method of suppressing junction capacitance of the source/drain regions is disclosed in this invention. The source/drain regions are formed by double implantation of phosphorus ions and arsenic ions. The phosphorus ion implantation lowers the energy needed in the implantation of arsenic ions, and reduces dislocations in the source/drain regions formed during implanting arsenic ions. Further, the double implantation suppresses the junction profile of arsenic ions, and enhances the width of depletion regions. So, the junction capacitance is reduced, thereby accelerate the function of semiconductor devices.

Abstract translation: 在本发明中公开了抑制源/漏区的结电容的方法。 源极/漏极区域通过磷离子和砷离子的双重注入而形成。 磷离子注入降低了砷离子注入所需的能量，并且减少了在注入砷离子时形成的源/漏区中的位错。 此外，双重注入抑制了砷离子的结型子，并增加了耗尽区的宽度。 因此，结电容减小，从而加速半导体器件的功能。