公开(公告)号：US10319641B2

公开(公告)日：2019-06-11

申请号：US16127241

申请日：2018-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L21/308 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.

公开(公告)号：US10312353B2

公开(公告)日：2019-06-04

申请号：US16212700

申请日：2018-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/06 ,  H01L27/092 ,  H01L21/02 ,  H01L21/225 ,  H01L21/8238

Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

公开(公告)号：US20190109050A1

公开(公告)日：2019-04-11

申请号：US16200670

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

公开(公告)号：US10204981B2

公开(公告)日：2019-02-12

申请号：US15656802

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Ching-Ling Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

公开(公告)号：US20180374757A1

公开(公告)日：2018-12-27

申请号：US16127241

申请日：2018-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/308

Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.

公开(公告)号：US10163659B1

公开(公告)日：2018-12-25

申请号：US15654552

申请日：2017-07-19

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/48 ,  H01L21/8234 ,  H01L29/66

Abstract: A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.

公开(公告)号：US20180331219A1

公开(公告)日：2018-11-15

申请号：US15627427

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L27/088 ,  H01L29/6656

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

公开(公告)号：US20180203344A1

公开(公告)日：2018-07-19

申请号：US15436764

申请日：2017-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chia-Hung Lin

IPC: G03F1/58 ,  G03F1/54

CPC classification number: G03F1/58 ,  G03F1/54

Abstract: A photomask includes a substrate, a patterned absorber layer disposed on the substrate, and a plurality of openings. Each of the openings penetrates the patterned absorber layer and exposes a part of the substrate. At least two of the openings are disposed adjacent to each other in a first direction. At least a part of the patterned absorber layer disposed between the two adjacent openings in the first direction has a first thickness. A part of the patterned absorber layer disposed at two opposite edges of each of the openings in a second direction different from the first direction has a second thickness. Another part of the patterned absorber layer disposed at the two opposite edges of each of the openings in the second direction has a third thickness. The first thickness is equal to the second thickness, and the first thickness is different from the third thickness.

公开(公告)号：US20180149978A1

公开(公告)日：2018-05-31

申请号：US15361085

申请日：2016-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/308 ,  G03F7/40

CPC classification number: H01L21/0274 ,  G03F7/0035 ,  G03F7/203

Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.

公开(公告)号：US09964866B2

公开(公告)日：2018-05-08

申请号：US15065872

申请日：2016-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Yi-Ting Chen ,  Chia-Hung Wang ,  Yi-Jing Wang

IPC: G06F17/50 ,  G03F9/00

CPC classification number: G03F9/7003

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.