公开(公告)号：US06468853B1

公开(公告)日：2002-10-22

申请号：US09641389

申请日：2000-08-18

申请人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

发明人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

IPC分类号： H01L218238

CPC分类号： H01L21/76235

摘要： A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate. A thermal oxidation step is performed converting the poly film into silicon oxide which slightly extends the STI field oxide into the active device region eliminating any reduced oxide coverage or oxide recesses in the corner regions.

摘要翻译： 描述了在浅沟槽隔离结构的角上制造具有改善的氧化物覆盖的半导体器件的结构和工艺。 使用衬垫氧化物和氮化硅层作为图案化元件来蚀刻STI沟槽。 在沟槽蚀刻之后，非晶，外延或多晶硅的薄的共形层沉积在氮化硅上并在沟槽内并退火。 当硅沉积在开口沟槽的硅底部和侧面上时，退火有效地形成单晶或外延硅。 接下来，在保形硅层上生长氧化硅衬垫。 然后用氧化硅填充沟槽，通过化学机械抛光或蚀刻对该结构进行平面化，并且去除氮化物和衬垫氧化物。在填充氧化物的垂直边缘上留下多晶硅膜，其在 硅衬底。 执行热氧化步骤，将多晶硅膜转化为将STI场氧化物稍微延伸到有源器件区域中的氧化硅，消除角区域中任何减少的氧化物覆盖或氧化物凹陷。

公开(公告)号：US06461900B1

公开(公告)日：2002-10-08

申请号：US09981438

申请日：2001-10-18

申请人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

公开(公告)号：US06461887B1

公开(公告)日：2002-10-08

申请号：US10038391

申请日：2002-01-03

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2100

CPC分类号： H01L21/76232

摘要： A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.

摘要翻译： 一种形成倒置阶梯状STI结构的方法，包括以下步骤。 提供具有上覆氧化物层的半导体衬底。 衬底具有至少一对在其间限定STI区的有源区。 首先在有源区内蚀刻氧化物层以形成第一级沟槽。 第一级沟槽具有暴露的侧壁。 连续的侧壁间隔件形成在所述暴露的第一阶梯沟槽侧壁上。 使用先前形成的步骤侧壁间隔物作为掩模，将氧化物层连续蚀刻X + 1次，以在有效区域内形成连续的台阶沟槽。 每个连续的台阶沟槽具有暴露的侧壁并且具有连续形成在连续的阶梯槽暴露侧壁上的侧壁间隔物。 使用先前形成的步骤侧壁间隔物作为掩模来最后蚀刻氧化物层，以形成在活性区域内暴露衬底的最终步骤沟槽。 STI区域包括倒置的阶梯状STI结构。 从X + 2台阶沟槽中移除台阶侧壁间隔物。 平面化的有源区硅结构形成在X + 2和最后阶梯沟内。

公开(公告)号：US06436774B1

公开(公告)日：2002-08-20

申请号：US09769811

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

公开(公告)号：US06403485B1

公开(公告)日：2002-06-11

申请号：US09846177

申请日：2001-05-02

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21302

CPC分类号： H01L21/76895

摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.

摘要翻译： 描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。 分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。 多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。 在每个栅电极的侧壁上形成电介质间隔物。 沉积覆盖栅电极和衬底的多晶硅层。 在硬掩模层上用抛光光阑抛光多晶硅层。 多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。 此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。 如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。 去除硬掩模层。 离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

公开(公告)号：US06303449B1

公开(公告)日：2001-10-16

申请号：US09713835

申请日：2000-11-16

申请人： Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Kiok Boone Quek ,  Ravi Sundaresan

发明人： Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Kiok Boone Quek ,  Ravi Sundaresan

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/2257 ,  H01L29/66492

摘要： A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer portions of the first insulating layer define the gate opening. A gate dielectric layer is formed over the substrate in the gate opening. A conductive layer is formed over the substrate. The conductive layer fills the gate opening and the source/drain (S/D) openings. The conductive layer is doped with dopants. The conductive layer is planarized to form a gate over the gate dielectric layer and filling the gate opening and filling the source/drain (S/D) opening to form elevated source/drain (S/D) regions. The conductive layer is preferably planarized so that the top surface of the conductive layer is level with the top surface of the first insulating layer. The spacer portions are removed to form spacer openings. LDD regions are formed in the substrate in the spacer opening. A dielectric layer is formed over the substrate filling the spacer openings. Source/drain (S/D) regions are formed in the substrate under the elevated source/drain (S/D) regions.

摘要翻译： 制造自对准提升源/漏（S / D）的方法。 第一绝缘层形成在衬底上。 第一绝缘层至少具有与开口相邻的栅极开口和源极/漏极（S / D）开口。 第一绝缘层的间隔部分限定了开口。 在栅极开口中的衬底上方形成栅极电介质层。 导电层形成在衬底上。 导电层填充栅极开口和源极/漏极（S / D）开口。 导电层掺杂有掺杂剂。 导电层被平坦化以在栅极介电层上形成栅极，并填充栅极开口并填充源极/漏极（S / D）开口以形成升高的源极/漏极（S / D）区域。 导电层优选被平坦化，使得导电层的顶表面与第一绝缘层的顶表面平齐。 间隔部分被去除以形成间隔开口。 LDD区域形成在衬垫开口中的衬底中。 介质层形成在填充间隔开口的衬底上。 在升高的源极/漏极（S / D）区域的衬底中形成源/漏（S / D）区。

公开(公告)号：US06277700B1

公开(公告)日：2001-08-21

申请号：US09480272

申请日：2000-01-11

申请人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L21/31116

摘要： A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

摘要翻译： 一种在栅极结构旁边蚀刻氮化硅间隔物的方法，包括：在衬底上的栅氧化层上提供栅电极。 衬底氧化物层设置在衬底和栅电极之上。 在衬垫氧化物层上提供氮化硅层。 本发明的氮化物蚀刻配方在等离子体蚀刻器中进行，以各向异性地蚀刻氮化硅层以产生间隔物。 氮化物蚀刻配方包括主蚀刻步骤和过蚀刻步骤。 主蚀刻步骤包括以下条件：在35和55摩尔％之间的Cl 2流动，He流动在35和55摩尔％之间，背面He压力在4和10托之间; 7.5至12.5摩尔％的HBr流量; 压力在400至900 mTorr之间; 功率在300至600瓦之间。 蚀刻配方提供了约1：1的间隔物宽度与氮化物层厚度比，并且不会沉积Si衬底表面。

公开(公告)号：US06248006B1

公开(公告)日：2001-06-19

申请号：US09490155

申请日：2000-01-24

申请人： Madhusudan Mukhopadhyay ,  Subramanian Balakumar ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

发明人： Madhusudan Mukhopadhyay ,  Subramanian Balakumar ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： B24B508

CPC分类号： B24B37/20 ,  B24B37/26 ,  B24B57/02

摘要： A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished.

摘要翻译： 提供了允许半导体表面的均匀抛光的新设备。 传统CMP方法的单个抛光垫被分成分裂垫，分离垫允许跨晶片表面的CMP控制参数的单独调整。 这些调整可以从晶片的中心延伸到其周边（沿着晶片的半径），从而可以消除抛光表面的中心与表面周边之间的抛光不均匀的常规问题 那是抛光。