公开(公告)号：US07142459B2

公开(公告)日：2006-11-28

申请号：US11301189

申请日：2005-12-12

申请人： Theodore T. Pekny ,  Steve Gualandri

发明人： Theodore T. Pekny ,  Steve Gualandri

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3481

摘要： A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted to perform a method of programming one or more of the flash memory cells when the external voltage exceeds a predetermined value and when the command control circuit receives a program command. The method includes, in response to the program command and the detected external voltage, applying an internally-generated programming voltage to a control gate of the one or more flash memory cells and applying a voltage pulse to a drain of the one or more flash memory cells while the control gate is at the internally-generated programming voltage.

公开(公告)号：US07006382B2

公开(公告)日：2006-02-28

申请号：US11136145

申请日：2005-05-24

申请人： Theodore T. Pekny ,  Steve Gualandri

发明人： Theodore T. Pekny ,  Steve Gualandri

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3481

摘要： A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted to perform a method of programming one or more of the flash memory cells when the external voltage exceeds a predetermined value and when the command control circuit receives a program command. The method includes, in response to the program command and the detected external voltage, applying an internally-generated programming voltage to a control gate of the one or more flash memory cells and applying a voltage pulse to a drain of the one or more flash memory cells while the control gate is at the internally-generated programming voltage.

公开(公告)号：US06992931B2

公开(公告)日：2006-01-31

申请号：US10230578

申请日：2002-08-29

申请人： Theodore T. Pekny

发明人： Theodore T. Pekny

IPC分类号： G11C16/04

CPC分类号： G11C16/3468

摘要： A reference cell programming system comprising a memory device and a tester. The memory device includes a memory array having at least one non-volatile reference cell and a sense amplifier coupled to sense a cell current conducted by the reference cell. The tester is coupled to the memory to program the reference cells to a designated charge level. Moreover, the tester provides a reference current that is coupled to the sense amplifier and monitors an output of the sense amplifier.

公开(公告)号：US06898122B2

公开(公告)日：2005-05-24

申请号：US10903398

申请日：2004-07-30

申请人： Theodore T. Pekny

发明人： Theodore T. Pekny

IPC分类号： G11C5/14 ,  G11C16/00

CPC分类号： G11C5/146

摘要： An improved voltage reduction circuit and method is described that incorporates an independently controllable back bias voltage for increased gate/bulk fields in isolation well voltage reduction transistors that couple to and reduce external voltages that are too high for the integrated circuit process technology limits. The improved voltage reduction circuit and method allows for a higher overall available voltage and current flow for regulation by the circuit. Additionally, the improved voltage reduction circuit and method reduces voltage reduction circuit size by allowing for efficient implementation in a single isolation well. Furthermore, the improved voltage reduction circuit and method includes a back bias voltage control circuit that turns on and regulates the back bias voltage and avoids the problem of reverse bias conditions.

公开(公告)号：US06731551B2

公开(公告)日：2004-05-04

申请号：US10192390

申请日：2002-07-10

申请人： Theodore T. Pekny

发明人： Theodore T. Pekny

IPC分类号： G11C700

CPC分类号： G11C29/26 ,  G11C2029/1202 ,  G11C2029/2602

摘要： A method and apparatus is provided for testing a memory portion using a stress signal. The method comprises identifying a first and second portion of a memory, wherein a stress signal is to be applied to only the second portion of the memory. The first portion is isolated from exposure to a stress signal. A stress signal is provided to the second portion of said memory for testing said second portion of memory. The first portion of said memory is isolated from said stress signal. The method further comprises performing an alternate wordline testing process.

摘要翻译： 提供一种用于使用应力信号测试存储器部分的方法和装置。 该方法包括识别存储器的第一和第二部分，其中应力信号仅被施加到存储器的第二部分。 第一部分与暴露于应激信号隔离。 应力信号被提供给所述存储器的第二部分，用于测试所述第二部分存储器。 所述存储器的第一部分与所述应力信号隔离。 该方法还包括执行替代字线测试过程。

公开(公告)号：US06714458B2

公开(公告)日：2004-03-30

申请号：US10074453

申请日：2002-02-11

申请人： Stephen J. Gualandri ,  Theodore T. Pekny

发明人： Stephen J. Gualandri ,  Theodore T. Pekny

IPC分类号： G11C1614

CPC分类号： G11C16/16

摘要： An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.

公开(公告)号：US06477082B2

公开(公告)日：2002-11-05

申请号：US09751688

申请日：2000-12-29

申请人： Theodore T. Pekny ,  Stephen J. Gualandri

发明人： Theodore T. Pekny ,  Stephen J. Gualandri

IPC分类号： G11C1134

CPC分类号： G11C16/08 ,  G11C7/1006 ,  G11C8/12

摘要： A memory device has a segmented memory cell array that take a row address and a column address and allows for data words in a column page to be read internally in parallel for faster access. The memory device employs a segmented memory array that routes column address and column address+1 to the segments. This allows for a random starting data word in the column page, while the data words in the next column page (column address+1) are loaded into the memory array segments before the starting data word. When the data page mode or linear burst access crosses a column address boundary the next data words in column address+1 are available and no wait states need to be asserted to allow for new column address values to propagate.

公开(公告)号：US06438032B1

公开(公告)日：2002-08-20

申请号：US09818426

申请日：2001-03-27

申请人： Theodore T. Pekny ,  Stephen J. Gualandri

发明人： Theodore T. Pekny ,  Stephen J. Gualandri

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C2216/18

摘要： A non-volatile memory generates a pump voltage from a voltage source, which is typically a charge pump circuit or alternative source. The memory includes a non-volatile memory array having a plurality of memory cells. The pump voltage is utilized to erase or program the floating gate memory cells. After the non-volatile memory device completes an erase or programming operation, the pump voltage source is disabled. A discharge control circuit gradually discharges all of, or the initial component of, a remaining programming voltage charge to ground. The discharge control circuit, therefore, reduces noise caused by a large discharge current spike in the non-volatile memory device.

摘要翻译： 非易失性存储器从电压源产生泵浦电压，电压源通常是电荷泵电路或替代源。 存储器包括具有多个存储单元的非易失性存储器阵列。 泵电压用于擦除或编程浮动栅极存储单元。 在非易失性存储器件完成擦除或编程操作之后，泵电压源被禁止。 放电控制电路将剩余编程电压电荷的全部或初始分量逐次放电至地。 因此，放电控制电路降低了由非易失性存储器件中的大放电电流尖峰引起的噪声。

公开(公告)号：US08694860B2

公开(公告)日：2014-04-08

申请号：US13735789

申请日：2013-01-07

申请人： Theodore T. Pekny ,  Victor Y. Tsai ,  Peter S. Feeley

发明人： Theodore T. Pekny ,  Victor Y. Tsai ,  Peter S. Feeley

IPC分类号： G11C29/00

CPC分类号： G06F13/4291 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F11/1064 ,  G06F11/1068 ,  G11C7/1006 ,  G11C16/26 ,  G11C2207/104 ,  G11C2207/2245 ,  G11C2216/30

摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

摘要翻译： 公开了一种用于操作NAND存储器件的方法和系统。 通过从主机向NAND存储器件发送串行外设接口信号来操作NAND存储器件，由此将信号传送到NAND存储器件中的NAND存储器，而不将信号修改为标准NAND存储器格式。 类似地，公开了用于从NAND存储器件接收信号而不将来自标准NAND格式的信号修改成串行格式的方法和系统。 该系统还包括错误检测和校正技术来检测和校正存储在NAND存储器件中的数据中的错误。

公开(公告)号：US08687422B2

公开(公告)日：2014-04-01

申请号：US13357533

申请日：2012-01-24

申请人： Theodore T. Pekny ,  Victor Y. Tsai

发明人： Theodore T. Pekny ,  Victor Y. Tsai

IPC分类号： G11C11/34

CPC分类号： G11C7/1021 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/145 ,  G06F13/1694 ,  G06F2212/1052 ,  G11C7/1072

摘要： A method and device are provided for operating in a special mode using a special mode enable register. In one example, a memory device includes registers in volatile memory and a memory array. At least one of the registers may include a special mode bit that controls a special mode of operation of the memory device.

摘要翻译： 提供了一种使用特殊模式使能寄存器在特殊模式下运行的方法和装置。 在一个示例中，存储器件包括易失性存储器中的寄存器和存储器阵列。 寄存器中的至少一个可以包括控制存储器件的特殊工作模式的特殊模式位。