-
公开(公告)号：US20120294085A1
公开(公告)日：2012-11-22
申请号：US13561519
申请日：2012-07-30
IPC分类号： G11C16/10
摘要： A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.
摘要翻译： 用于并发操作的多分区存储器和架构通过为多个分区提供公共读取读出放大器和程序路径来减少电路开销。 用于读取和算法操作的长单独数据允许在单个存储器块中并行操作和阻止多个操作。
-
2.发明授权Regulating voltages for refresh operation using flash trim bits in semiconductor memory devices 有权使用半导体存储器件中的闪光修整位调整刷新操作的电压公开(公告)号：US07352643B2
公开(公告)日：2008-04-01
申请号：US11619414
申请日：2007-01-03
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/147 , G11C7/1045 , G11C16/12 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/0407
摘要： A method and apparatus for regulating voltages in semiconductor devices. Trim bits are stored in a trim flash array, where the trim bits define a voltage value and where the voltage value is accessible once a control signal representing a word line signal is provided to the trim flash array reaches a selected voltage level. A refresh signal is provided to a voltage regulator in response to the control signal reaching the selected level, causing the voltage regulator to change its regulation value to that defined by the trim bits. A signal at a voltage level represented by the voltage value is provided to a memory array that is accessed based on the provided signal.
摘要翻译： 一种用于调节半导体器件中的电压的方法和装置。 修整位存储在修整闪存阵列中，其中修剪位定义电压值，并且一旦将表示字线信号的控制信号提供给修整闪光阵列，电压值就可以访问，达到选定的电压电平。 响应于控制信号达到所选择的电平，将一个刷新信号提供给电压调节器，使得电压调节器将其调节值改变为由修整位定义的调节值。 将由电压值表示的电压电平的信号提供给基于所提供的信号被存取的存储器阵列。
-
公开(公告)号：US08233322B2
公开(公告)日：2012-07-31
申请号：US10683075
申请日：2003-10-10
IPC分类号： G11C16/04
摘要： A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.
摘要翻译： 用于并发操作的多分区存储器和架构通过为多个分区提供公共读取读出放大器和程序路径来减少电路开销。 用于读取和算法操作的长单独数据允许在单个存储器块中并行操作和阻止多个操作。
-
4.发明授权High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices 有权闪存器件中的高电压正，负两相放电系统和通道擦除方法公开(公告)号：US06868016B2
公开(公告)日：2005-03-15
申请号：US10768573
申请日：2004-01-29
CPC分类号： G11C16/16
摘要： An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
摘要翻译： 闪速存储器中的擦除放电电路耦合到阵列源和p阱驱动器并且接收第一和第二放电信号。 擦除放电电路响应于第一放电信号在第一模式的放电周期期间操作，以将第一节点耦合到第二节点，并以第一速率对第一和第二节点上的电压进行放电。 擦除放电电路响应于第二放电信号在第二模式下工作，以将第一节点耦合到第二节点，以第二速率放电第一节点和第二节点上的电压。
-
5.发明授权High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices 有权闪存器件中的高电压正，负两相放电系统和通道擦除方法公开(公告)号：US07200047B2
公开(公告)日：2007-04-03
申请号：US11080351
申请日：2005-03-14
CPC分类号： G11C16/16
摘要： An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
摘要翻译： 闪速存储器中的擦除放电电路耦合到阵列源和p阱驱动器并且接收第一和第二放电信号。 擦除放电电路响应于第一放电信号在第一模式的放电周期期间操作，以将第一节点耦合到第二节点，并以第一速率对第一和第二节点上的电压进行放电。 擦除放电电路响应于第二放电信号在第二模式下工作，以将第一节点耦合到第二节点，以第二速率放电第一节点和第二节点上的电压。
-
公开(公告)号：US06714458B2
公开(公告)日：2004-03-30
申请号：US10074453
申请日：2002-02-11
IPC分类号： G11C1614
CPC分类号： G11C16/16
摘要： An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase discharge circuit operates during a discharge cycle in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The erase discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate.
-
公开(公告)号：US06477082B2
公开(公告)日：2002-11-05
申请号：US09751688
申请日：2000-12-29
IPC分类号： G11C1134
CPC分类号： G11C16/08 , G11C7/1006 , G11C8/12
摘要： A memory device has a segmented memory cell array that take a row address and a column address and allows for data words in a column page to be read internally in parallel for faster access. The memory device employs a segmented memory array that routes column address and column address+1 to the segments. This allows for a random starting data word in the column page, while the data words in the next column page (column address+1) are loaded into the memory array segments before the starting data word. When the data page mode or linear burst access crosses a column address boundary the next data words in column address+1 are available and no wait states need to be asserted to allow for new column address values to propagate.
-
公开(公告)号：US06438032B1
公开(公告)日：2002-08-20
申请号：US09818426
申请日：2001-03-27
IPC分类号： G11C1604
CPC分类号： G11C16/12 , G11C5/145 , G11C2216/18
摘要： A non-volatile memory generates a pump voltage from a voltage source, which is typically a charge pump circuit or alternative source. The memory includes a non-volatile memory array having a plurality of memory cells. The pump voltage is utilized to erase or program the floating gate memory cells. After the non-volatile memory device completes an erase or programming operation, the pump voltage source is disabled. A discharge control circuit gradually discharges all of, or the initial component of, a remaining programming voltage charge to ground. The discharge control circuit, therefore, reduces noise caused by a large discharge current spike in the non-volatile memory device.
摘要翻译： 非易失性存储器从电压源产生泵浦电压，电压源通常是电荷泵电路或替代源。 存储器包括具有多个存储单元的非易失性存储器阵列。 泵电压用于擦除或编程浮动栅极存储单元。 在非易失性存储器件完成擦除或编程操作之后，泵电压源被禁止。 放电控制电路将剩余编程电压电荷的全部或初始分量逐次放电至地。 因此，放电控制电路降低了由非易失性存储器件中的大放电电流尖峰引起的噪声。
-
公开(公告)号：US07173869B2
公开(公告)日：2007-02-06
申请号：US10917608
申请日：2004-08-13
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/147 , G11C7/1045 , G11C16/12 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/0407
摘要： The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first voltage level using a voltage regulator, determining that a second voltage level is desired and initializing the voltage regulator to provide the second voltage level based on determining that the second voltage level is desired.
摘要翻译： 本发明提供一种用于调节半导体器件中的电压的方法和装置。 该方法和装置包括使用电压调节器提供第一电压电平，确定期望第二电压电平，并且基于确定期望第二电压电平来初始化电压调节器以提供第二电压电平。
-
公开(公告)号：US06937517B2
公开(公告)日：2005-08-30
申请号：US10197782
申请日：2002-07-18
CPC分类号： H02M3/07 , H02M2001/0032 , Y02B70/16
摘要： The present invention provides a method and apparatus for regulating clocks for varying loads. The method includes providing a regulated signal of a first amplitude during a first operating mode and a regulated signal of a second amplitude during a second operation mode. The method further includes driving at least one of a first load and a second load based on the regulated signal.
摘要翻译： 本发明提供一种用于调节负载变化的时钟的方法和装置。 该方法包括在第一操作模式期间提供第一幅度的调节信号和在第二操作模式期间提供第二幅度的调节信号。 该方法还包括基于经调节的信号驱动第一负载和第二负载中的至少一个。
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.019 秒)
