公开(公告)号：US5913045A

公开(公告)日：1999-06-15

申请号：US576452

申请日：1995-12-20

申请人： Byron Gillespie ,  Scott Tetrick ,  Bruce Young

发明人： Byron Gillespie ,  Scott Tetrick ,  Bruce Young

IPC分类号： G06F13/24 ,  G06F13/00 ,  G06F9/46

CPC分类号： G06F13/24

摘要： An element of a multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge (P2P). The invention is part of a design that consolidates a high performance processor (the local processor) and other processing elements into a single system which utilizes a local memory. Four PCI interrupt inputs are provided which can be routed to either local processor interrupt inputs or to PCI Interrupt output pins. In this manner, a server designer is able to connect the PCI interrupts directly to the local processor without any jumpers to provide configuration. Additionally, by providing software which would execute on the local processor, the local processor system can intercept the PCI interrupts and process the low level interrupts to create an intelligent I/O subsystem. A simple multiplexor is used to direct the PCI interrupts inputs to the local processor or directs the PCI interrupt inputs directly to the PCI interrupt outputs. The PCI interrupt inputs would be interrupts from PCI devices connected to the secondary PCI bus or PCI add-in cards connected to the secondary PCI bus. The PCI outputs would go directly to an interrupt controller which supports the host processor interrupt structure. This PCI interrupt output mechanism supports the ability to have the local processor intercept the PCI interrupts, determine if the local processor should process the interrupt or forward the interrupt upstream to the host.

摘要翻译： 将高性能处理器集成到PCI到PCI总线桥（P2P）中的多功能设备的元件。 本发明是将高性能处理器（本地处理器）和其他处理元件合并为利用本地存储器的单个系统的设计的一部分。 提供了四个PCI中断输入，可以将其连接到本地处理器中断输入或PCI中断输出引脚。 以这种方式，服务器设计人员能够将PCI中断直接连接到本地处理器，而无需任何跳线来提供配置。 另外，通过提供将在本地处理器上执行的软件，本地处理器系统可以拦截PCI中断并处理低级中断以创建智能I / O子系统。 一个简单的多路复用器用于将PCI中断输入引导到本地处理器，或将PCI中断输入直接引导到PCI中断输出。 PCI中断输入将是连接到辅助PCI总线的PCI设备或连接到辅助PCI总线的PCI附加卡的中断。 PCI输出将直接连接到支持主机处理器中断结构的中断控制器。 这种PCI中断输出机制支持本地处理器拦截PCI中断的能力，确定本地处理器是否应该处理中断或将中断转发到主机。

公开(公告)号：US5832241A

公开(公告)日：1998-11-03

申请号：US878660

申请日：1997-06-19

申请人： Charles B. Guy ,  Bruce Young ,  Norman Rasmussen

发明人： Charles B. Guy ,  Bruce Young ,  Norman Rasmussen

IPC分类号： G06F13/40 ,  H01J13/00

CPC分类号： G06F13/4004

摘要： A bus bridge is disclosed that handles bus transactions that must be completed on a destination bus before being completed on an originating bus by indicating a retry to delay such bus transactions on the originating bus while completing such bus transactions on the destination bus.

摘要翻译： 公开了一种总线桥，其处理在通过始发总线完成之前必须在目的地总线上完成的总线事务，通过在目的地总线上完成这样的总线事务处指示重试来延迟始发总线上的总线事务。

公开(公告)号：US5559954A

公开(公告)日：1996-09-24

申请号：US413922

申请日：1995-03-29

申请人： Thomas Y. Sakoda ,  Bruce Young

发明人： Thomas Y. Sakoda ,  Bruce Young

IPC分类号： G09G5/02 ,  G09G5/06 ,  G06F12/00

CPC分类号： G09G5/06 ,  G09G5/02 ,  G09G2340/0407

摘要： A host processor system is capable of executing a plurality of application programs and generating multi-format pixels for display on a computer display monitor in accordance with the application programs. The host processor system also generates a format map comprising a plurality of format identifiers wherein each format identifier specifies a format type for at least one multi-format pixel. The host processor system transfers multiformat pixel data and the format map to a multi-format frame buffer corresponding to a display monitor. The multi-format frame buffer is coupled to random access memory (RAM) digital to analog converter (DAC). During a blanking period of the display monitor, the format map is transferred from the multi-format frame buffer to a memory in the RAM DAC. The RAM DAC converts the format of each multi-format pixel a format compatible with the display monitor. One of the display compatible formats is selected based on the format identifier specifying the format type for that particular multi-format pixel as described by the format map. The selected multi-format pixel is then converted to an analog signal to control the graphics of the display monitor.

摘要翻译： 主处理器系统能够执行多个应用程序并且根据应用程序生成用于在计算机显示监视器上显示的多格式像素。 主处理器系统还生成包括多个格式标识符的格式图，其中每个格式标识符指定至少一个多格式像素的格式类型。 主处理器系统将多格式像素数据和格式图传输到对应于显示监视器的多格式帧缓冲器。 多格式帧缓冲器耦合到随机存取存储器（RAM）数模转换器（DAC）。 在显示监视器的消隐期间，格式图从多格式帧缓冲器传送到RAM DAC中的存储器。 RAM DAC将每个多格式像素的格式转换为与显示监视器兼容的格式。 基于格式标识符来选择显示兼容格式之一，该格式标识符指定格式图所描述的特定多格式像素的格式类型。 然后将所选择的多格式像素转换为模拟信号以控制显示监视器的图形。

公开(公告)号：US5467295A

公开(公告)日：1995-11-14

申请号：US876577

申请日：1992-04-30

申请人： Bruce Young ,  Dave Carson ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

发明人： Bruce Young ,  Dave Carson ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

IPC分类号： G06F13/364 ,  G06F13/36

CPC分类号： G06F13/364

摘要： A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.

摘要翻译： 一种计算机总线，其使得总线主控代理能够向/从从属代理发送/接收数据的突发，而不事先确定要传送的数据字的数量，或甚至可以传送的最大数量的数据字。 主机，从机或总线仲裁器可以随时以最小的开销终止突发。 此外，主机或从机可以通过添加等待状态来抑制数据传输的速度。 分布式地址解码由耦合到总线的每个代理执行。 每个代理人必须要求主人指示的交易。 如果没有代理人在预定数量的时钟周期内要求交易，减法解码设备可以默认地要求交易。 总线还包括总线锁，其中每个总线从属代理可能能够进入锁定状态，并且一旦处于锁定状态，则拒绝除了被锁定的主代理发起的所有访问之外的所有访问。 信号线LOCK＃一次只由一个主代理拥有。 虽然LOCK＃信号必须通过在LOCK＃为高电平时获取总线而获得，但只要LOCK＃保持低电平，就保持线路的所有权。 因此，主代理可以拥有锁，而另一个主机使用总线。

公开(公告)号：US07874881B1

公开(公告)日：2011-01-25

申请号：US12541440

申请日：2009-08-14

申请人： Luis Sosa ,  Robert Hobbs ,  Bruce Young

发明人： Luis Sosa ,  Robert Hobbs ,  Bruce Young

IPC分类号： H01R4/10

CPC分类号： H01R4/188 ,  Y10T29/49208

摘要： An improved full tension connector for electrical conductors has a substantially cylindrical outer surface and a stepped series of substantially cylindrical inner surfaces with progressively smaller inside diameters. The design of the connector allows for improved control of the compression of the cable inside the fitting. A series of swages, progressing successively from a light compression to a heavier compression, ensures that the connector will sustain the required tensile load.

摘要翻译： 用于电导体的改进的全张力连接器具有基本上圆柱形的外表面和具有逐渐更小的内径的基本上圆柱形的内表面的阶梯系列。 连接器的设计允许改进对配件内的电缆的压缩的控制。 从轻压缩到较重的压缩，连续进行的一系列措施确保连接器能够承受所需的拉伸载荷。

公开(公告)号：US06434644B1

公开(公告)日：2002-08-13

申请号：US09587408

申请日：2000-06-05

申请人： Bruce Young ,  Corwyn Richard Meyer

发明人： Bruce Young ,  Corwyn Richard Meyer

IPC分类号： B06F300

CPC分类号： G06F13/385

摘要： A system and method for communicating information between an information handling system and a peripheral device of the information handling system are disclosed. A processor is coupled to a bus for carrying information provided by the processor, and a host controller coupled to the bus receives the information and sends the information to the peripheral device according to a first communications standard. A peripheral device controller coupled to the host controller converts the information from the first communications standard to a second communications standard and transmits the information to the peripheral device in accordance with the second communications standard interpretable by the peripheral device. Control information is generated and sent to a peripheral device controller according to a first communications standard. The control information is converted from the first communication standard to a second communication standard and transmitted to the peripheral. The peripheral device receives and interprets the control information and executes a control function.

摘要翻译： 公开了一种用于在信息处理系统和信息处理系统的外围设备之间传送信息的系统和方法。 处理器耦合到总线以承载由处理器提供的信息，并且耦合到总线的主机控制器接收信息并根据第一通信标准将信息发送到外围设备。 耦合到主控制器的外围设备控制器将来自第一通信标准的信息转换为第二通信标准，并根据由外围设备可解释的第二通信标准将信息发送到外围设备。 生成控制信息并根据第一通信标准将其发送到外围设备控制器。 控制信息从第一通信标准转换为第二通信标准并传送到外围设备。 外围设备接收并解释控制信息并执行控制功能。

公开(公告)号：US6115796A

公开(公告)日：2000-09-05

申请号：US806524

申请日：1997-02-24

申请人： George Hayek ,  Ali S. Oztaskin ,  Brian Langendorf ,  Bruce Young

发明人： George Hayek ,  Ali S. Oztaskin ,  Brian Langendorf ,  Bruce Young

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F12/0835 ,  G06F13/1684 ,  G06F13/4059

摘要： A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

摘要翻译： 公开了具有集成总线桥和存储器控制器电路和方法的计算机系统，该电路和方法能够访问具有高带宽数据流的共享存储器。 集成总线桥接器和存储器控制器电路在通过第二总线发起到共享存储器的访问事务期间通过第一总线执行一系列前置提前事务，从而实现第二总线上的高带宽数据流传输。 集成总线桥接器和存储器控制器电路包括外围写入缓冲器，其缓冲通过第二总线接收的写入数据，并且存储用于写入数据的窥探完成标志，该数据指示用于写入数据的对应的窥探事件是否完成。 集成总线桥接器和存储器控制器电路还包括一个外设读取预取缓冲器，只有在读取数据的相应窥探事件完成之后，才能通过第二总线在读取事务期间预取读取数据。

公开(公告)号：US5941964A

公开(公告)日：1999-08-24

申请号：US480953

申请日：1995-06-07

申请人： Bruce Young ,  Jeff Rabe ,  Stephen Fischer

发明人： Bruce Young ,  Jeff Rabe ,  Stephen Fischer

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/405

摘要： A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge. In response to an interrupt signal from an agent on a bus, the bridge control unit flushes posted data before allowing a processor to process the interrupt signal. The bridge control unit further requires that the bridge complete all posted writes generated from a first bus before the bridge accepts a read generated from a second bus. The bridge control unit additionally insures strict ordering of accesses through the bridge. Data consistency is thereby realized without requiring the bridge to participate in the cache coherency protocol of the primary bus.

摘要翻译： 公开了一种拦截同步事件并有选择地刷新桥内缓冲器中的数据的总线桥。 该桥通过主动拦截同步事件，包括中断，控制状态寄存器的处理器访问和共享存储空间的I / O主机访问来保证数据一致性。 中断信号可以通过桥接器路由，其包括由用于管理通过桥接器的数据传输的状态机逻辑组成的桥接控制单元。 响应于来自总线上的代理的中断信号，桥接控制单元在允许处理器处理中断信号之前刷新发布的数据。 桥接控制单元还要求桥接器在桥接受从第二总线产生的读取之前，完成从第一总线产生的所有发布的写入。 桥梁控制单元另外确保通过桥梁的严格顺序访问。 从而实现数据一致性，而不需要桥接器来参与主总线的高速缓存一致性协议。

公开(公告)号：US5887194A

公开(公告)日：1999-03-23

申请号：US472069

申请日：1995-06-05

申请人： Dave Carson ,  Bruce Young ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

发明人： Dave Carson ,  Bruce Young ,  Norman Rasmussen ,  Stephen Fischer ,  Jeffrey Rabe

IPC分类号： G06F13/364 ,  G06F13/14 ,  G06F13/20

CPC分类号： G06F13/364

摘要： A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.

摘要翻译： 一种计算机总线，其使得总线主控代理能够向/从从属代理发送/接收数据的突发，而不事先确定要传送的数据字的数量，或甚至可以传送的最大数量的数据字。 主机，从机或总线仲裁器可以随时以最小的开销终止突发。 此外，主机或从机可以通过添加等待状态来抑制数据传输的速度。 分布式地址解码由耦合到总线的每个代理执行。 每个代理人必须要求主人指示的交易。 如果没有代理人在预定数量的时钟周期内要求交易，减法解码设备可以默认地要求交易。 总线还包括总线锁，其中每个总线从属代理可能能够进入锁定状态，并且一旦处于锁定状态，则拒绝除了被锁定的主代理发起的所有访问之外的所有访问。 信号线LOCK＃一次只由一个主代理拥有。 虽然LOCK＃信号必须通过在LOCK＃为高电平时获取总线而获得，但只要LOCK＃保持低电平，就保持线路的所有权。 因此，主代理可以拥有锁，而另一个主机使用总线。

公开(公告)号：US5835784A

公开(公告)日：1998-11-10

申请号：US611802

申请日：1996-03-06

申请人： Byron Gillespie ,  Bruce Young

发明人： Byron Gillespie ,  Bruce Young

IPC分类号： G06F13/36 ,  G06F1/10 ,  G06F9/445 ,  G06F13/40 ,  G06F13/42 ,  G06F15/177

CPC分类号： G06F13/4045 ,  G06F1/10

摘要： A method and system for booting a first processor from a remote memory. In response to a reset signal, a processor which has no associated local memory is prevented from executing code and particularly its boot sequence. Because the first processor is prevented from initializing its environment, configuration cycles from a host processor should be prevented from configuring that environment until the first processor has booted. By preventing the host processor from configuring, the first processor environment's integrity is protected. Because the first processor has no local memory, address cycles generated to access local memory would normally go unclaimed on a local bus. An interface between the local bus and the remote memory is configured to claim the local memory address range from the local bus. Once the first processor is enabled, the local memory addresses are used to access the remote memory to return the necessary boot code.

摘要翻译： 一种用于从远程存储器引导第一处理器的方法和系统。 响应于复位信号，防止没有关联的本地存储器的处理器执行代码，特别是其启动顺序。 由于第一个处理器无法初始化其环境，因此应防止从主机处理器的配置周期配置该环境，直到第一个处理器启动为止。 通过防止主机处理器的配置，第一处理器环境的完整性受到保护。 因为第一个处理器没有本地存储器，所以产生访问本地存储器的地址周期通常在本地总线上无人认领。 本地总线和远程存储器之间的接口被配置为从本地总线声明本地存储器地址范围。 启用第一个处理器后，本地内存地址将用于访问远程内存以返回必要的启动代码。