摘要:
A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.
摘要:
A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.
摘要:
A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it. Signal line LOCK# is owned by only one master agent at a time. Although the LOCK# signal must be obtained by acquiring the bus while LOCK# is high, ownership of the line is maintained as long as LOCK# is held low. Therefore, a master agent can own the lock while another master uses the bus.
摘要:
A bus bridge which intercepts synchronization events and selectively flushes data in buffers within the bridge is disclosed. The bridge insures data consistency by actively intercepting synchronization events, including, interrupts, processor accesses of a control status registers, and I/O master accesses of shared memory space. Interrupt signals may be routed through the bridge, which includes a bridge control unit comprised of state machine logic for managing data transfers through the bridge. In response to an interrupt signal from an agent on a bus, the bridge control unit flushes posted data before allowing a processor to process the interrupt signal. The bridge control unit further requires that the bridge complete all posted writes generated from a first bus before the bridge accepts a read generated from a second bus. The bridge control unit additionally insures strict ordering of accesses through the bridge. Data consistency is thereby realized without requiring the bridge to participate in the cache coherency protocol of the primary bus.
摘要:
A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.
摘要:
A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要:
A method and system for internal data loop back in a packet switch is provided. In some instances, the switch may be required to process multiple layers of a header within the data packet, such as when data is transferred over the network encapsulated with a TCP header at the Transport Layer to form a TCP packet, then encapsulated with an IP header at the Network Layer to form an IP packet, then encapsulated with one or more MPLS headers to form a MPLS packet, and then encapsulated with an Ethernet header at the Link Layer to form an Ethernet packet. In such an instance, the data packet can be iteratively processed by the packet switch using an internal loop back technique. An internal loop back may be accomplished by using a header providing internal routing instructions resulting in the data packet being routed directly from an egress queue back to an ingress queue whereupon the lower levels of the header can be processed.
摘要:
A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.
摘要:
The present invention provides compounds of formula I: in which: one of T1 and T4 is N and the other is C; T2 and T3 are independently N or C(CH2)nR2; X, Y and Z are independently N or C(CH2)nR3; R1 is Ar1 or R1 is C1-6alkyl optionally substituted with one or two groups Ar1; Ar1 is an optionally substituted cyclohexyl, piperidinyl, piperazinyl, morpholinyl, adamantyl, phenyl, naphthyl, a six membered heteroaromatic ring containing one, two or three nitrogen atoms, a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one O or S atom being present, or a nine- or ten-membered bicyclic heteroaromatic ring in which phenyl or a six-membered heteroaromatic ring as defined above is fused to a six- or five-membered heteroaromatic ring as defined above; Ar is an optionally substituted phenyl, a six-membered heteroaromatic ring containing one, two or three nitrogen atoms or a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one heteroatom being O or S, Ar being optionally substituted by one, two or three groups chosen from halogen, CF3, OCF3, C1-6-alkyl, C2-6alkenyl, C2-6alkynyl, nitro, cyano, isonitrile, hydroxy, C1-6alkoxy, C1-6alkylthio, —NR6R7, —CONR6R7, —COH, CO2H, C1-6alkoxycarbonyl, haloC1-4alkyl, hydroxyC1-6alkyl, aminoC1-6alkyl, C1-4alkylcarbonyl and a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one heteroatom being O or S, optionally substituted by C1-6alkyl, halogen, amino, hydroxy or cyano; or a pharmaceutically acceptable salt thereof as a VR-1 ligand; pharmaceutical compositions comprising it; its use in therapy; use of it in the manufacture of a medicament to treat pain; and methods of treating subjects suffering from pain.
摘要:
A dynamic directory and tetrahedralization method. The dynamic directory of degree of freedom data for elements in a non-conformal mixed-element mesh includes elements subdividable into tetrahedral, in which a respective degree of freedom value is stored for each element, wherein the degree of freedom value is current as element subdivision proceeds. The tetrahedralization method includes providing a non-conformal mixed element mesh comprising elements subdividable into tetrahedra, identifying respective degree of freedom values for the elements in the mesh, and performing element subdivision based on the degree of freedom values of elements in the mesh.