公开(公告)号：US08045405B2

公开(公告)日：2011-10-25

申请号：US11779349

申请日：2007-07-18

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

摘要翻译： 公开了一种存储器系统，存储器和存储器系统命令协议。 在存储器系统内，存储器控制器向存储器传送命令，该命令从包括写入命令和多个非写入命令的一组命令中选择。 在指示写入命令的数字值和指示多个非写入命令中的任何一个的数字值之间计算的汉明距离值大于1。

公开(公告)号：US08037390B2

公开(公告)日：2011-10-11

申请号：US11862409

申请日：2007-09-27

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： H03M13/00

CPC分类号： G06F11/1008

摘要： A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

摘要翻译： 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US08020068B2

公开(公告)日：2011-09-13

申请号：US11779345

申请日：2007-07-18

申请人： Jung-Bae Lee

发明人： Jung-Bae Lee

IPC分类号： H03M13/00

CPC分类号： G06F11/1008

摘要： A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

公开(公告)号：US20110199836A1

公开(公告)日：2011-08-18

申请号：US12958726

申请日：2010-12-02

申请人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

发明人： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC分类号： G11C29/12 ,  G11C7/10

CPC分类号： G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

摘要翻译： 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US20090085650A1

公开(公告)日：2009-04-02

申请号：US12325846

申请日：2008-12-01

申请人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

发明人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC分类号： G05F3/02

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

摘要翻译： 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US07219274B2

公开(公告)日：2007-05-15

申请号：US10831702

申请日：2004-04-23

申请人： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

发明人： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

IPC分类号： G11C29/04 ,  G11C29/48

CPC分类号： G11C29/14 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

摘要： A memory module, including a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.

摘要翻译： 一种存储器模块，包括用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出 正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。

公开(公告)号：US07200067B2

公开(公告)日：2007-04-03

申请号：US10895554

申请日：2004-07-21

申请人： Mee-Hyun Ahn ,  Jung-Bae Lee

发明人： Mee-Hyun Ahn ,  Jung-Bae Lee

IPC分类号： G11C9/00

CPC分类号： H01L23/50 ,  G11C5/025 ,  G11C2207/105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

摘要翻译： 一种半导体存储器件，包括能够减少用于在单元阵列中读取和写入数据的数据路径的控制焊盘和输入/输出I / O焊盘，以及用于驱动半导体存储器件的方法。 半导体存储器件包括布置在存储器芯片的单元区域的多个存储器组，以及多个控制焊盘和多个I / O焊盘，这些控制焊盘和多个I / O焊盘在存储芯片处彼此分开布置，用于读/写数据 来自/在存储体中，其中多个控制焊盘和I / O焊盘分散在相邻存储体之间的周边区域和存储体的外部。

公开(公告)号：US07145828B2

公开(公告)日：2006-12-05

申请号：US11105169

申请日：2005-04-12

申请人： Yun-Sang Lee ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US20060083079A1

公开(公告)日：2006-04-20

申请号：US11252535

申请日：2005-10-18

申请人： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

发明人： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC分类号： G11C16/04

CPC分类号： G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

摘要： A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

摘要翻译： 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。