公开(公告)号：US20050243627A1

公开(公告)日：2005-11-03

申请号：US11105169

申请日：2005-04-12

申请人： Yun-Sang Lee ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US07145828B2

公开(公告)日：2006-12-05

申请号：US11105169

申请日：2005-04-12

申请人： Yun-Sang Lee ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US20060018174A1

公开(公告)日：2006-01-26

申请号：US11169241

申请日：2005-06-27

申请人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

发明人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US06826115B2

公开(公告)日：2004-11-30

申请号：US10640146

申请日：2003-08-13

申请人： Jung-Bae Lee ,  Yun-Sang Lee

发明人： Jung-Bae Lee ,  Yun-Sang Lee

IPC分类号： G11C800

CPC分类号： G11C7/1021 ,  G11C8/10 ,  G11C8/12

摘要： A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.

公开(公告)号：US08042404B2

公开(公告)日：2011-10-25

申请号：US12128159

申请日：2008-05-28

申请人： Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

发明人： Young-Chan Jang ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC分类号： G01L1/00

CPC分类号： G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

摘要： A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

摘要翻译： 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US07894241B2

公开(公告)日：2011-02-22

申请号：US12326940

申请日：2008-12-03

申请人： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Woo-Jung Sun ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

摘要： A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

摘要翻译： 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US07164615B2

公开(公告)日：2007-01-16

申请号：US11169241

申请日：2005-06-27

申请人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

发明人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US20080295605A1

公开(公告)日：2008-12-04

申请号：US12128159

申请日：2008-05-28

申请人： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

发明人： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC分类号： G01B7/16

CPC分类号： G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

摘要： A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

摘要翻译： 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US07196941B2

公开(公告)日：2007-03-27

申请号：US10798469

申请日：2004-03-11

申请人： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

发明人： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C7/10 ,  G11C7/1021 ,  G11C7/1048 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

摘要翻译： 一种半导体存储器件和用于从其读取和读取数据的方法包括：存储单元阵列，包括连接在多个字线和多个位线对之间的多个存储器单元，预定数量的写入线对 ，预定数量的读线对，用于在写入操作期间在多个位线对与预定数量的写入线对之间传送数据的多个写入列选择门和用于发送数据的多个读取列选择门 在读取操作期间在多个位线对与预定数量的读取线对之间。 因此，可以通过数据输入焊盘和数据输出焊盘同时输入和输出数据。

公开(公告)号：US09183910B2

公开(公告)日：2015-11-10

申请号：US13907223

申请日：2013-05-31

申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。