公开(公告)号：US06301692B1

公开(公告)日：2001-10-09

申请号：US09153063

申请日：1998-09-15

申请人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

发明人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  H01L27/11807

摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

摘要翻译： 首先，将给定逻辑电路分为组合电路部分和寄存器部分。 通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。 每个部分电路被转换成具有晶体管电平的电路。 然后，产生具有晶体管电平的部分电路的布局单元。 此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。 因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。 特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。 因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。 另外，可以确保面积减少，低功耗，高速运转等优点。

公开(公告)号：US06249450B1

公开(公告)日：2001-06-19

申请号：US09458894

申请日：1999-12-10

申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

IPC分类号： G11C1500

CPC分类号： G11C7/106 ,  G06F12/0893 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/043 ,  G11C2207/2245

摘要： A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

公开(公告)号：US6025669A

公开(公告)日：2000-02-15

申请号：US34118

申请日：1998-03-03

申请人： Yasuhiro Tanaka

发明人： Yasuhiro Tanaka

IPC分类号： H01L41/047 ,  H03H9/13 ,  H01L41/08

CPC分类号： H03H9/131 ,  H01L41/0475 ,  H01L41/0477

摘要： A piezoelectric resonator which can be used as part of a piezoelectric component prevents self-welding of electrodes provided on the surface of a piezoelectric and which include silver with silver coated terminals with which the electrodes abut by forming high fusion point metals on the electrodes. The high fusion point metals include Ni, Cr, W, Ti, Mo, Ni--Cu (monel) or their alloy. The thickness of the high fusion point metal is preferably less than about 1/10 of the thickness of the electrode or less than 1 .mu.m.

摘要翻译： 可以用作压电元件的一部分的压电谐振器防止设置在压电体表面上的电极的自焊接，并且其中包括具有银涂覆端子的银，其电极通过在电极上形成高熔点金属而邻接。 高熔点金属包括Ni，Cr，W，Ti，Mo，Ni-Cu（monel）或它们的合金。 高熔点金属的厚度优选小于电极厚度的约+ E，fra 1/10 + EE或小于1μm。

公开(公告)号：US5875148A

公开(公告)日：1999-02-23

申请号：US454118

申请日：1995-06-02

申请人： Yasuhiro Tanaka ,  Satoru Tanoi

发明人： Yasuhiro Tanaka ,  Satoru Tanoi

IPC分类号： G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： H01L27/10897 ,  G11C11/4085 ,  G11C8/08 ,  G11C8/14 ,  H01L27/10891

摘要： A plurality of memory cell arrays each having a plurality of memory cells and a plurality of word lines the word lines are driven by drive circuits which share the driving operation, and permit reading out from and writing into the memory cells connected to the word lines WL to be driven. These drive circuits are respectively connected to main word lines WLO, which are driven by decoding the entered address information in a decoding circuit whereby the drive circuits are driven. Since the main word lines WLO are formed with a third metal wiring layer, a wiring of the word lines can be formed with a gate wiring layer of a transistor and a first metal wiring layer and wiring of a line control circuit can be formed with a second metal wiring layer which intersects the word lines thereby reducing delay operation of the memory.

摘要翻译： PCT PCT / JP94 / 00115 Sec。 371日期：1995年6月2日 102（e）1995年6月2日PCT 1994年1月28日PCT PCT。 出版物WO94 / 17554 日期1994年8月4日多个存储单元阵列，每个存储单元阵列具有多个存储单元和多个字线，字线由共享驱动操作的驱动电路驱动，并且允许从连接的存储单元读出和写入 到要驱动的字线WL。 这些驱动电路分别连接到主字线WLO，它们通过在驱动电路驱动的解码电路中解码输入的地址信息来驱动。 由于主字线WLO由第三金属布线层形成，所以字线的布线可以由晶体管的栅极布线层和第一金属布线层形成，并且线路控制电路的布线可以形成有 与字线相交的第二金属布线层，从而减少存储器的延迟操作。

公开(公告)号：US5824951A

公开(公告)日：1998-10-20

申请号：US680627

申请日：1996-07-17

申请人： Yasuhiro Tanaka

发明人： Yasuhiro Tanaka

IPC分类号： H03H9/02 ,  H01L23/10 ,  H03H9/10 ,  H03H9/13 ,  H03H9/17 ,  H01L23/02

CPC分类号： H03H9/1028 ,  H01L23/10 ,  H01L2924/0002

摘要： The invention provides an electronic part which includes a casing having a recessed portion which is free of accumulation of moisture and gases and in which a piezoelectric element and terminals are received, and a lid sealably covering the recessed portion. The casing and the lid are respectively provided with narrow grooves communicating with the recessed portion. The casing and the lid are welded together by a ultrasonic welding method at their peripheral edges with the exception of the narrow grooves and portions outside thereof, thereby forming a very narrow gap between the casing and the lid.

摘要翻译： 本发明提供了一种电子部件，其包括具有凹部的壳体，该凹部没有水分和气体的积聚，并且其中容纳有压电元件和端子，并且盖子可密封地覆盖凹部。 壳体和盖分别设置有与凹部连通的窄槽。 壳体和盖子通过超声波焊接方法在其外围边缘处焊接在一起，除了窄槽和其外部的部分，从而在壳体和盖子之间形成非常窄的间隙。

公开(公告)号：US5684641A

公开(公告)日：1997-11-04

申请号：US570639

申请日：1995-12-11

申请人： Yasuhiro Tanaka ,  Osamu Doi ,  Kenji Inoue ,  Jun Murata ,  Michihiro Yamagata

发明人： Yasuhiro Tanaka ,  Osamu Doi ,  Kenji Inoue ,  Jun Murata ,  Michihiro Yamagata

IPC分类号： G02B13/00 ,  G02B3/06 ,  G02B13/08 ,  G11B7/125 ,  G11B7/135 ,  G02B3/02 ,  G11B7/00

CPC分类号： G02B3/06 ,  G11B7/1374 ,  G11B7/1398

摘要： In an objective lens for an optical head apparatus for reading or writing an information on a recording medium such as optical disc, astigmatism is added on axial wavefront aberration so that off-axis astigmatism is to be cancelled by the axial astigmatism. At least one surface of the objective lens is a toric or cylindrical surface, and a standard deviation of astigmatism component of axial wavefront aberration is defined as Wa is to be restricted in a range of 0

摘要翻译： 在用于在诸如光盘之类的记录介质上读取或写入信息的光学头装置的物镜中，在轴向波前像差上增加像散，使得通过轴向像散消除离轴散光。 物镜的至少一个表面是复曲面或圆柱形表面，并且将轴向波面像差的像散分量的标准偏差定义为在0

公开(公告)号：US5596521A

公开(公告)日：1997-01-21

申请号：US365970

申请日：1994-12-29

申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/00

CPC分类号： G11C7/106 ,  G06F12/0893 ,  G11C11/4096 ,  G11C15/04 ,  G11C15/043 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/2245

摘要： A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

摘要翻译： 半导体存储器件具有用于存储数据的存储器单元，用于放大所存储的数据的读出放大器，以及可放置放大数据以用于快速调用的高速缓存单元。 高速缓存单元可以在存储单元刷新周期期间继续保持数据，从而允许快速访问缓存的数据。 高速缓存单元可以耦合到可以从读出放大器断开的列数据线，使得能够刷新存储器单元，同时缓存访问正在进行。 可以提供写入缓冲器，使得当高速缓存数据被替换时，旧的高速缓存数据可以被复制回存储器单元，同时正在访问新的高速缓存数据。

公开(公告)号：US5577223A

公开(公告)日：1996-11-19

申请号：US297450

申请日：1994-08-29

申请人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

发明人： Satoru Tanoi ,  Yasuhiro Tanaka ,  Tetsuya Tanabe

IPC分类号： G06F12/08 ,  G11C11/401 ,  G11C11/408 ,  G06F12/00

CPC分类号： G11C11/4087 ,  G06F12/0893

摘要： A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

摘要翻译： 一种具有TAG块中的TAG地址保持电路的动态RAM，其与多个子阵列中的一个子阵列对应以保持X（行）地址的低位。 TAG块中的块控制电路根据所保存的地址确定“命中”或“小号”，并响应于子地址确定新的X地址并输出TAG确定信号。 响应于TAG判断信号，子阵列控制电路传送用于访问TAG块和列读出放大器的信号。 当确定“命中”时，列读出放大器用作高速缓存，并且锁存在列读出放大器中的数据在数据总线上读出。

公开(公告)号：US5535058A

公开(公告)日：1996-07-09

申请号：US109532

申请日：1993-08-20

申请人： Yasuhiro Tanaka ,  Michihiro Yamagata

发明人： Yasuhiro Tanaka ,  Michihiro Yamagata

IPC分类号： G02B3/06 ,  G02B13/00 ,  G02B13/18 ,  G11B7/09 ,  G11B7/135

CPC分类号： G02B3/06 ,  G11B7/0909 ,  G11B7/1378

摘要： An optical system for detecting a focus error signal in an optical disc according to the astigmatic method is constituted by a single lens element. This lens element has a first lens surface defined by a toric surface effective to converge the incident rays of light and also to produce an astigmatism. This lens element also has a second lens surface which has a negative power so as to form a telephoto optical system, making it possible to shorten the length of the optical system.

摘要翻译： 用于根据像散法检测光盘中的聚焦误差信号的光学系统由单个透镜元件构成。 该透镜元件具有由复曲面表面限定的第一透镜表面，其有效地会聚入射光线并且还产生像散。 该透镜元件还具有第二透镜表面，该第二透镜表面具有负的功率以形成远摄光学系统，使得可以缩短光学系统的长度。

公开(公告)号：US5511030A

公开(公告)日：1996-04-23

申请号：US296364

申请日：1994-08-24

申请人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

发明人： Yasuhiro Tanaka ,  Tetsuya Tanabe ,  Satoru Tanoi

IPC分类号： G11C11/401 ,  G11C7/12 ,  G11C7/18 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C11/409 ,  G11C7/12 ,  G11C7/18

摘要： A semiconductor memory device according to the present invention is constructed in such a manner that two first and second memory circuits are respectively electrically connected to one sense amplifier provided between the memory circuits through changeover elements and equalize elements are electrically connected to their corresponding bit line pairs included in the memory circuits. Owing to this construction, an operation for resetting the bit line pair in the first memory circuit and the sense amplifier after completion of access to the first memory circuit and an operation for reading data into the bit line pair in the second memory circuit can be performed so as to overlap each other in time. It is therefore possible to obtain quick-access to the second memory circuit.

摘要翻译： 根据本发明的半导体存储器件被构造成使得两个第一和第二存储器电路分别通过切换元件电连接到设置在存储器电路之间的一个读出放大器，并且均衡元件电连接到它们对应的位线对 包含在存储器电路中。 由于这种结构，可以执行用于在完成对第一存储器电路的访问之后复位第一存储器电路中的位线对和读出放大器的操作以及用于将数据读入第二存储器电路中的位线对的操作 以便在时间上彼此重叠。 因此可以获得对第二存储器电路的快速访问。