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    Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof
    1.
    发明授权
    Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
    用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法

    公开(公告)号：US06301692B1

    公开(公告)日：2001-10-09

    申请号：US09153063

    申请日：1998-09-15

    申请人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    发明人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022 ,  G06F17/5068 ,  H01L27/11807

    摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

    摘要翻译： 首先，将给定逻辑电路分为组合电路部分和寄存器部分。 通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。 每个部分电路被转换成具有晶体管电平的电路。 然后，产生具有晶体管电平的部分电路的布局单元。 此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。 因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。 特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。 因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。 另外，可以确保面积减少，低功耗，高速运转等优点。

    Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof
    2.
    发明授权
    Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
    用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法

    公开(公告)号：US5983008A

    公开(公告)日：1999-11-09

    申请号：US153333

    申请日：1998-09-15

    申请人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    发明人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    IPC分类号： G06F17/50 ,  H01L27/118

    CPC分类号： G06F17/5022 ,  G06F17/5068 ,  H01L27/11807

    摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

    摘要翻译： 首先，将给定逻辑电路分为组合电路部分和寄存器部分。 通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。 每个部分电路被转换成具有晶体管电平的电路。 然后，产生具有晶体管电平的部分电路的布局单元。 此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。 因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。 特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。 因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。 另外，可以确保面积减少，低功耗，高速运转等优点。

    Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof
    3.
    发明授权
    Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof 失效
    通过用于验证其定时的相同方法和方法获得的半导体集成电路半导体集成电路布局的设计方法

    公开(公告)号：US5923569A

    公开(公告)日：1999-07-13

    申请号：US732808

    申请日：1996-10-15

    申请人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    发明人： Shinichi Kumashiro ,  Hiroshi Mizuno ,  Yasuhiro Tanaka ,  Toshiyuki Moriwaki ,  Youichirou Mae

    IPC分类号： G06F17/50 ,  H01L27/118

    CPC分类号： G06F17/5022 ,  G06F17/5068 ,  H01L27/11807

    摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.

    摘要翻译： 首先，将给定逻辑电路分为组合电路部分和寄存器部分。 通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。 每个部分电路被转换成具有晶体管电平的电路。 然后，产生具有晶体管电平的部分电路的布局单元。 此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。 因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。 特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。 因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。 另外，可以确保面积减少，低功耗，高速运转等优点。

    Method and apparatus for data path circuit layout design and memory medium for causing computer to execute data path circuit layout design
    4.
    发明授权
    Method and apparatus for data path circuit layout design and memory medium for causing computer to execute data path circuit layout design 失效
    用于数据路径电路布局设计和存储介质的方法和装置，用于使计算机执行数据路径电路布局设计

    公开(公告)号：US5737237A

    公开(公告)日：1998-04-07

    申请号：US602315

    申请日：1996-02-16

    申请人： Yasuhiro Tanaka ,  Hiroshi Mizuno ,  Shinichi Kumashiro

    发明人： Yasuhiro Tanaka ,  Hiroshi Mizuno ,  Shinichi Kumashiro

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The present invention provides a data path circuit layout design method capable of generating a mask layout which satisfies timing specifications and given contour conditions, and which is reduced in circuit area. There are prepared function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells. For a data path circuit of which function blocks are described by function macros, the placement of the function blocks is optimized by a function macro placement process. By a function macro expansion process, the function macros describing the function blocks are expanded and connection information on the schematic leaf cell level are prepared. By a detail placement and routing process, the schematic leaf cells are replaced with the corresponding layout leaf cells and the layout leaf cells are wired to one another, thereby to generate a mask layout of the data path circuit.

    摘要翻译： 本发明提供一种数据路径电路布局设计方法，其能够产生满足定时规格和给定轮廓条件并且电路面积减小的掩模布局。 准备了功能宏，其中每个功能宏根据参数定义了包括多个示意性叶单元的电路的扩展。 对于通过功能宏描述功能块的数据路径电路，通过功能宏放置过程优化功能块的布局。 通过功能宏扩展过程，扩展了描述功能块的功能宏，并准备了原理图单元格级别的连接信息。 通过详细的放置和布线过程，用相应的布局叶单元替换示意图叶单元，并且将布局叶单元相互连接，从而生成数据路径电路的掩码布局。

    Lighting control device and lighting control method
    6.
    发明授权
    Lighting control device and lighting control method 失效
    照明控制装置和照明控制方法

    公开(公告)号：US08710746B2

    公开(公告)日：2014-04-29

    申请号：US13608370

    申请日：2012-09-10

    申请人： Toshiaki Takahashi ,  Yasushi Morimoto ,  Kenji Takahashi ,  Yukio Ishida ,  Hitoshi Kawano ,  Shinichi Kumashiro ,  Sayaka Kikuta

    发明人： Toshiaki Takahashi ,  Yasushi Morimoto ,  Kenji Takahashi ,  Yukio Ishida ,  Hitoshi Kawano ,  Shinichi Kumashiro ,  Sayaka Kikuta

    IPC分类号： H05B37/02

    CPC分类号： H05B37/0227 ,  Y02B20/44

    摘要： In the lighting control device according to the exemplary embodiment, the detection section detects the presence or absence of a person in a lighting area and a movement speed of a person, based on an image data of the lighting area that is lighted by a light source of a plurality of lighting apparatuses and is acquired from an imaging device. A decision section decides whether each of division areas is a stay area or a non-stay area based on the movement speed of a person detected by the detection section. A lighting control section performs different lighting controls on the lighting apparatus of the division area decided as the stay area by the decision section and the lighting apparatus of the division area decided as the non-stay area.

    摘要翻译： 在根据示例性实施例的照明控制装置中，检测部基于由光源照明的照明区域的图像数据来检测人的照明区域的存在或不存在以及人的移动速度 的多个照明装置，并且从成像装置获取。 决定部基于检测部检测到的人的移动速度来判定分割区域是否为停留区域或非停留区域。 照明控制部分通过决定部分和被判定为非停留区域的分割区域的照明装置对被判定为停留区域的划分区域的照明装置执行不同的照明控制。

    Power Supply Device and Lighting Device
    7.
    发明申请
    Power Supply Device and Lighting Device 审中-公开
    电源设备和照明设备

    公开(公告)号：US20130106311A1

    公开(公告)日：2013-05-02

    申请号：US13599283

    申请日：2012-08-30

    申请人： Go Kato ,  Shinichiro Matsumoto ,  Hiromichi Nakajima ,  Masahiko Kamata ,  Shinichi Kumashiro ,  Hitoshi Kawano ,  Koji Takahashi

    发明人： Go Kato ,  Shinichiro Matsumoto ,  Hiromichi Nakajima ,  Masahiko Kamata ,  Shinichi Kumashiro ,  Hitoshi Kawano ,  Koji Takahashi

    IPC分类号： H05B37/02 ,  H02M3/26

    CPC分类号： H05B33/0815 ,  H02M2001/0006

    摘要： According to one embodiment, in a power supply device, a power conversion circuit which outputs a power supply voltage to a load by converting the power supply voltage into a predetermined output voltage, and control circuit which has a ground potential which is different from that of the power conversion circuit, and controls the power conversion circuit are provided. In addition, a power supply circuit which supplies the power supply voltage to the control circuit by converting the power supply voltage into a control power supply which is insulated with respect to the ground voltage of the power conversion circuit.

    摘要翻译： 根据一个实施例，在电源装置中，电力转换电路通过将电源电压转换为预定的输出电压而将电源电压输出到负载，以及控制电路，其具有与 电源转换电路，并且控制电源转换电路。 另外，电源电路通过将电源电压转换为相对于电力转换电路的接地电压绝缘的控制电源，将电源电压提供给控制电路。